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5 Commits

Author SHA1 Message Date
David Daney
612663a974 MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h 
The internal codes are not part of the kernel's ABI.

Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4932/
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2013-02-20 18:24:24 +01:00
Ralf Baechle
0bc1c15735 MIPS: Export <asm/break.h>. 
It always should have been ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2013-01-16 16:57:27 +01:00
David Daney
c1bf207d6e MIPS: kprobe: Add support. 
This patch is based on previous work by Sony and Himanshu Chauhan.

I have done some cleanup and implemented JProbes and KRETPROBES.  The
KRETPROBES part is pretty much copied verbatim from powerpc.  A possible
future enhance might be to factor out the common code.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: Himanshu Chauhan <hschauhan@nulltrace.org>
To: linux-mips@linux-mips.org
To: ananth@in.ibm.com,
To: anil.s.keshavamurthy@intel.com
To: davem@davemloft.net
To: masami.hiramatsu.pt@hitachi.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1525/
Patchwork: https://patchwork.linux-mips.org/patch/1530/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2010-08-05 13:26:29 +01:00
Ralf Baechle
ba3049ed40 MIPS: Switch FPU emulator trap to BREAK instruction. 
Arguably using the address error handler has always been ugly.  But with
processors that handle unaligned loads and stores in hardware the
current mechanism ceases to work so switch it to a BREAK instruction and
allocate break code 514 to the FPU emulator.

Yoichi Yuasa provided a build fix for CONFIG_BUG=n.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
 2008-10-30 14:44:34 +00:00
Ralf Baechle
384740dc49 MIPS: Move headfiles to new location below arch/mips/include 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2008-10-11 16:18:52 +01:00