1 Commits

Author	SHA1	Message	Date
Elaine Zhang	f1c506d152	clk: rockchip: add clock controller for the RK3588 ... Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2022-11-15 11:37:41 +01:00