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MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
We've already been using the correct one in the non-div case, start
doing so for the other one as well.
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
GPUCC has its own GPLL0 leg, switch to it to allow shutting it down
when it's unused.
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-7-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add support for wlan-2g LED on GPIO 36 and wps buttons on GPIO 35.
Signed-off-by: Sridharan S N <quic_sridsn@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230616083238.20690-2-quic_sridsn@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
At the moment we define a single ov5640 sensor in the apq8016-sbc and
disable that sensor.
The sensor mezzanine for this is a D3 Engineering Dual ov5640 mezzanine
card. Move the definition from the apq8016-sbc where it shouldn't be to a
standalone dts.
Enables the sensor by default, as we are adding a standalone mezzanine
structure.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-7-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
There are two control lines controlled by GPIO going into ov5640
- Reset
- Powerdown
The driver and yaml expect "reset-gpios" and "powerdown-gpios" there has
never been an "enable-gpios".
Fixes: 39e0ce6cd1bf ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-6-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The driver for the ov5640 doesn't do a set-rate, instead it expects the
clock to already be set at an appropriate rate.
Similarly the yaml for ov5640 doesn't understand clock-frequency. Convert
from clock-rate to assigned-clock and assigned-clock-rate to remediate.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-5-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The yaml constraint for data-lanes is [1, 2] not [0, 2]. The driver itself
doesn't do anything with the data-lanes declaration save count the number
of specified data-lanes and calculate the link rate so, this change doesn't
have any functional side-effects.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-4-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The ov5640 driver expects DOVDD, AVDD and DVDD as regulator supply names.
The ov5640 has depended on these names since the driver was committed
upstream in 2017. Similarly apq8016-sbc.dtsi has had completely different
regulator names since its own initial commit in 2020.
Perhaps the regulators were left on in previous 410c bootloaders. In any
case today on 6.5 we won't switch on the ov5640 without correctly naming
the regulators.
Fixes: 39e0ce6cd1bf ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-3-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Each CSIPHY in CAMMS maps to a port here in the dtsi, since the number of
CSIPHYs is fixed per SoC define the 8916 ports for both available PHYs.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-2-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add MIPI-DSI support to Verdin AM62.
Verdin AM62 has a MIPI DSI interface on the edge connector, this is
provided with a Toshiba TC358778 DPI to MIPI-DSI bridge connected to the
DSS DPI port with a 18-bit width parallel bus.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230812191123.14779-1-francesco@dolcini.it
Signed-off-by: Nishanth Menon <nm@ti.com>
The only remaining consumer is new_inode, where it showed up in 2001 as
commit c37fa164f793 ("v2.4.9.9 -> v2.4.9.10") in a historical repo [1]
with a changelog which does not mention it.
Since then the line got only touched up to keep compiling.
While it may have been of benefit back in the day, it is guaranteed to
at best not get in the way in the multicore setting -- as the code
performs *a lot* of work between the prefetch and actual lock acquire,
any contention means the cacheline is already invalid by the time the
routine calls spin_lock(). It adds spurious traffic, for short.
On top of it prefetch is notoriously tricky to use for single-threaded
purposes, making it questionable from the get go.
As such, remove it.
I admit upfront I did not see value in benchmarking this change, but I
can do it if that is deemed appropriate.
Removal from new_inode and of the entire thing are in the same patch as
requested by Linus, so whatever weird looks can be directed at that guy.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git/commit/fs/inode.c?id=c37fa164f793735b32aa3f53154ff1a7659e6442 [1]
Signed-off-by: Mateusz Guzik <mjguzik@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588
also has two PCIe3 IP blocks, that will be handled separately.
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-neu6a, 6b
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230731165723.53069-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The ROCK Pi 4A, ROCK Pi 4B and ROCK Pi 4C boards contain a nor-flash chip
connected to spi1. Enable spi1 and add the device node.
This patch has been tested on ROCK Pi 4A.
Signed-off-by: Stefan Nagy <stefan.nagy@ixypsilon.net>
Link: https://lore.kernel.org/r/20230811201118.15066-1-stefan.nagy@ixypsilon.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The defined value for "status" is "disabled", not "disable".
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230804225813.12493-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just a single minor whitespace cleanup in couple of FVP device trees.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmTM07EACgkQAEG6vDF+
4phuBRAAjCgTXNN6z3ltpP3ukClpAesNg8U0IPQHV0gVJeyQSCjal9BrvHZr7gFI
Vt7Vd3YV8tUinmmHubRa3KXGV8E8xZZAJE2rTH5kht+WaLPSffrUoDMfYCGhiwc+
lioJsblKOYw5yUZ3QEV2lzHz/mAzU/3pl2adS2KEdiijLKA/amlXJLEO3XBzIZu9
UO2qRaES48zcAgYyfUkgokjJqnsiKMprWagA3r965cniWnTEA0S5cvYSXtLjYWdv
DJmKDn8n1oHVcx5JhYZjzr2ZH5f62XcriYbTozrSDYLccr4d+JfaMghXAo6vbg/9
9NBdXZzxpA1ddMxIdARZAMcJFYps+UnZM5ra1SxU7AK0oFhfNEwwgPRlDV5gZTwk
JomJn5VOr/VuqUA49KACFrQjPdBrS13cfqQY5Z3oBBv01t4TZMuCV0/4lC7O/FFR
t2J23CACjra/hD4WBOG/2pD4KLIxJHYLHkgGdptKdcN3KGYCDV6yR+jrV+0e5y1q
2DUIpawL4qLNA+wt2CCsOe4f+SVjTgiUBh6/fn7f0Oxdz8VeCe1MxryfoGNnELE9
q3AjIr9GtvUes9T9JR5zUBvfNbpb/Qs72CcKL8IHnoJGnMJkCm6wPtz/57MOefCp
sylmZaPGe1fE1S2KdLS09KQq7/ppyyxefZMbioMty8ffw2g3sho=
=3YVD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXRn4ACgkQYKtH/8kJ
Uid1HQ/9FlpJ+X4Q6rKv9jU2FF2ZYTCGBmbF9jajXhyY9jg2LKxWfV6RG03KN3FE
FlpLq+UwTjTFvYlk5Gegw262bK3RpqPxVb9EfOpCm1+DPisdCHoAbcYJ35GDeCUE
7xok26lGykakpPZClsmS7keKbtHwKQTtntvcpy9AZcfxBKwLVWACbMUHN09ZrztN
2tdgxd2/XRo1erigsY9MFGxLxkyjFqtYDenR/r7m50R89KnvNbsRfbPJDrUNeDYj
Jv8fnkW9bIT1XNWji2A6Dq3/uM78E2nP5CvgQgvgEHcBZsIg+enQo2fqFkFpajKs
1xy1XJlkecB1EQLsddWVaHei8mPS729wKzK4rn3M5+rHVWH4Ffj+dktLpysQixGC
JSPB8Mwunnb3XgtKmGL8TW2dmHFqhMM/Cmk6qhktTeS2cIXWswnm0E/aPgZ9EQLW
CBvWQyVczuQ/ahMnEsa4intXNexb6jWcPi+/wX4RMpFr5s/etyG51DDgMJVux2f/
+F/IEAEXYK6heb8GZcQD6Ro/aksTZ1weamTTHLnW2ceGkp7sSjqO3ydeynTJLnaN
KLah64bCg70v0yoHGgbbsZMphRWm9iSMfoEU60Ji2z+YgPP76b2MMwYj1V3txFb9
kd6QTP+iA4qRgD+70qjmvg19WOKDWtZCxkYjsX/DlVj17lft2sU=
=FqwV
-----END PGP SIGNATURE-----
Merge tag 'juno-update-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP update for v6.6
Just a single minor whitespace cleanup in couple of FVP device trees.
* tag 'juno-update-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: arm: minor whitespace cleanup around '='
Link: https://lore.kernel.org/r/20230804123223.3258086-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Miscellaneous fixes according the DTS coding style
- Correct the clocks order of the sd0 for the hi3798cv200
-----BEGIN PGP SIGNATURE-----
iQJJBAABCgAzFiEEQeMYD8qOQTc1R/snC8hXbtmJZlwFAmTMYsAVHHh1d2VpNUBo
aXNpbGljb24uY29tAAoJEAvIV27ZiWZcvsYP/3i2T7XnFR2KcGuASMbqgPRYTy4z
8Ehfu9+ubul6RqGMt5zSYBbYEHH6woxg85Rgpz7xEhi98y7MY+dIaZrpmLZ7JqmU
US6Rq2ADGACXPnJMhAJXBoUuKdH5NFapZdlIb95ao6bhpnH+Liyt6f078pFoFvLV
ZEzQupbDVd9u5DRN7wKxhG0oFboVsdrupwR7UY+vLKAx33BZH2CvLpCwlWJtiXEU
y7LvMsBzhoTUJADtsrRYUxSeck2gOx0seME+cRRD6/ElBvDAmyhZ8B4hW+lPaDRZ
YmY846ySoKWh+E3FI2vsqPcKPYQ8HobZvtcTvBpYuKNhUHBQWqXydcxeVUqsjvbT
7a2vVY1QxD0JPsUb4QzpbthlhLi2MobMIL7FqCxDIPW8jm55qIfL/jD81Tm6lteZ
c2/Mp1aX4wWnRR8T+er1aKflBqDGr51y1KhqZZb/tmLOKNEnFNrRz6+eVa2rMC1Y
Vr59nzptylswfrm7k6eEgTpqkwErxqSIjUJv+mUL0ms8oI3jBnM7nirzZOizuuNF
UU4xODRowh91nIjxwaJeWk7noWq66rUJtMuv24yIRneJHu3V6z/hkKA9GIFiezqx
zjBuFLKV9DqY9afc3m3Q2Ajtfb7NkZ0zAv8+GUHBSKKpOQ1NDsYYquinrit42k00
XKHPyXYr82IsnW7y
=T5Tw
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXRgQACgkQYKtH/8kJ
UieBZg//bDQbNyBOq62hVzCSKW0ruFa42ETJcJ7b+Exh9/VCRn5ZagIilPI6ux7U
ZNpjg8Rx/q/Q78BSxsz/YXsD9nCePFAPPbCLv7i1QfrWVElqC0klPXyfm5b3X8n3
LhtIgMkcHdzgmzOXgqVDMQ0h8AMqtJPECJvcIGMkBMiw0J3l8XuhGR4grFXp8V+q
xGNbnOh0h7hwxlhkDrveSXCxvDVMu9hVc5FdyU9eXPjJKB4rI7ZDUkRblHl/rM9S
o2dARhPkmgetFu7+mgx+BmR7FKTvn6nr/UMcIoeV979608PAEzWr1Of7GMQCgKOw
3MYhIoi2sCUKqz9yGLT0hFtOxtYcBq4LQ4VnyBV0anz5Q0HH1xneb/SYAdmZHCKJ
SCC3Ni/+HC+dnOM2Uyz2s++6Jf39qFpEdzhyrqhzXlcRZvz5V3g0xUhuAXATZO/w
5SFjTEzQQr/siOnvSJotlDYI0LbQGRPqYi3vf/0f0JiVJzzwGQaB2/8PUNw/C5JG
kXLVYxzTanYFSRGpWJO69RoJurJVBhgCA35viV4A20Rgj+MMyYLEAEHqssv+RrZx
MP0iZrexNXuBlrl50A6K+1uBfBgv//IlEvPtuX3VQP47ErWD9LvR3X6zrLOVv5GX
TBJuGH7phhqME2puhebN0chhaOSdL1KlR3e7isR70SpOe3M2VC0=
=CyEJ
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for v6.6
- Miscellaneous fixes according the DTS coding style
- Correct the clocks order of the sd0 for the hi3798cv200
* tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi:
arm64: dts: hi3798cv200: Fix clocks order of sd0
arm64: dts: hisilicon: add missing space before {
arm64: dts: hisilicon: minor whitespace cleanup around '='
Link: https://lore.kernel.org/r/64CC99A3.5030701@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
- Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
SMARC EVK development boards,
- Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
- Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
- Add LED support for the Spider development board,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZMOojAAKCRCKwlD9ZEnx
cDCFAPsHgAfrHWFiL0x6AhhNOesqKAWvplGhosT0zArv7TNZtwEAq5QXAy3xFHS6
v9HA2cskx4OaGCDrdNqz7DBj30IyZQM=
=mRJ6
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXRWAACgkQYKtH/8kJ
UidYHg//YGa4bHI8SOS40hlTQ6exi4/aHMfqgolVDUjRSVPn/gu+7QLza3ErmSTW
lHdm4IlkSFTk9OZTbVpbcsFnrv5vC5edMDhoKuV4n2rtu9iiHdBk23NqG+C9CGmC
4eEVq3Q17jMetoCN2R8hijhqjVKoGC3VZqMfY7wI0GcVGJkBIi/jZRMqVFBI/D0L
uk732qm6NgVWi49ZM5P1D2klZOhgJNNvgDcTLaB0BsvkSSodQP2WiaztC8jFB5gh
Ti/ie6UCCEevMRrnYzUUfc4lSWUCfkJ3oLt2a8s9FxFKiZQf9+9rYZ3sVQEy+emI
U48ZuEzf+7VQ+00zC9tuqgtOdjevoxjfCUMdcVd+j3AkjWc+PDWLxd90CYCA4Psu
EVk2MR6DdgWJHq1CdynlPPbUoDFTlNKrZ/Mn/8km5goLefUsOFbhheazcVBkLPgR
a9KY1BY/fP2J/1AvCIh5co5WrTrA5E4BcenHRzRINEzF69mCdESjkWGHaHRNaFc+
4sFrJWfoHHjIgxfbPbqGhOQJYOWwftcUOjZxU+V7W1T3Ptc3Eq89BhSjANH5UA3y
uAXgepbDs3cUd+F3NtARmMsUCMB4t7bG7vma2LdDqbYg819qDcMoDhGPJECHAOT4
TOxS8Ve5iiT7w4MiImy9pAqZPKbjX/GRq2XdTHClhKkbbZoL+GQ=
=GODg
-----END PGP SIGNATURE-----
Merge tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.6
- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
- Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
SMARC EVK development boards,
- Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
- Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
- Add LED support for the Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider-cpu: Add GP LEDs
arm64: dts: renesas: r8a779f0: Add INTC-EX node
arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
arm64: dts: renesas: r9a07g043: Add MTU3a node
ARM dts: renesas: armadillo800eva: Switch to enable-gpios
arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0
riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node
arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
arm64: dts: renesas: Add missing space before {
ARM: dts: renesas: Add missing space before {
arm64: dts: renesas: Minor whitespace cleanup around '='
arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: r9a09g011: Add CSI nodes
arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos
arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels
Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmTDh6gTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoScQEACE+qavOgmAWl86a7+Nohl6UpdWG7gF
jeDLlz6sO2BpOofGkPdwZ2YDltTfgg6LqA+zE+4+g04CQaGKcMLmmNUBBfKrBRqj
CFPfflkD58POUwr4RTR4pL/YzoQ9LTf2tXO2RMpcRpkb8UHkUgtWuno+nTZLKsrd
XdSZOSa8C2ufV7C0d1pSXP6tAkROlfBvMD1g1oGrbqwsl2OJ/U6mA8+jkTUdhMlU
uLf20MeIqyGJ99jT6c1o8mO39Y4aEOhYshSUMFnGuuNfDhj2PoASophfhhLOB4ov
N/cp9UszinkR9fy+7snhxAVofKh2Wj5EJLma8H9IAE+27qEFOM30CAQ4ijoD1I4s
XsveGeT2n5aakX8xij90TKRB7r9TC0mgmTWAA3AATVj0GJf6lCqaxjhuOb+8aAqT
OBddwTmdyjds+zAO/ksDzqMATk36tJbG0v3ZcifrBkaH6j9G6z5hgpDWb5I3mJLN
4MwLlZPfn3qkt0SKcpdBko+m1tNXzhD56sQJhTO1jj0Vz1gEHdYHWY5V8YRPUWyA
5t8v0c5e4diV3rRChmFzzArkB2aLw7AO2+UwVq9ToKXwC3pUud+aIQZEU+glrfPx
jCjR6QDeXEQEF5ZPhGaxI9n4qMr/LUPWlRdNaebh+t+2kPy905QGRGvOmornAvmW
vstAWFP3mINKdg==
=dFJV
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXRSgACgkQYKtH/8kJ
Uic1vg//fdLvrTE1GWu/U2Uzgfz+/fudOmAuHamb6M2fFIZ4kDPGPN9a9+gsfHbl
mHXfmDVAk1NgmXqfUvA8NyLpfcqxNxXrwufyumHAdpvb6G0F8KYPXnLgYJbjkQFd
AbwSZBJlxn/+hJqdFo+WFwx9XUr4qjGY85C6qp4ZsL6kxPmo387AMkwHvWEpblOj
cu6Itqb9GqxphdJeKcA2YYS7fdpXgAg6DJ78R4CaT5QeO5X6Xp/4fNOSbpGHl3vV
pnUlXATRXcrVyU8ER7RNo53n1oXSUAARb7RBN1Nm2L9YTf8lZa4dDJ1p4l72Mmei
x2AcOP1tpFGUkxui8IIOeXzgJHwQJTJwfrDu1blYuwcO4KuSS+YNO58DIu+osQVZ
7lLm2cOAifK/tS//v8tmBALUTC/tiJmOD+9JzaTzehxKOR5jY9VL48kcHTxO3xKU
60XMseMy7MdrHu69zVNr3gVZALLQWHZU9JfEv3n5eX6m1eI6TSXF4iQK46aMJT9D
vKSb0fDqeWfJhfyof4ZTP1QFhvED1KRSrC7sRuY14yv3iOoy/pTM/V/5f5PdAMXk
0SvUwIzZW48lCbv6HABthYYvwPfx/m+Y+vpF6/CrF9l3XiRmRmPJFba6EkpVaUJ4
zvyfPSbcYzjwK4+x/gKi2JanfZ9mCJaTtNqLQEc0VQZBcIjFj8Y=
=JIHb
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.6-rc1
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
* tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits)
arm64: tegra: Add blank lines for better readability
arm64: tegra: Remove {clock,reset}-names from VIC powergate
arm64: tegra: Drop incorrect maxim,disable-etr on Smaug
arm64: tegra: Add SPI device tree nodes for Tegra234
arm64: tegra: Enable UARTA and UARTE for Orin Nano
arm64: tegra: Add UARTE device tree node on Tegra234
arm64: tegra: Adapt to LP855X bindings changes
arm64: tegra: Add PCIe and DP 3.3V supplies
arm64: tegra: Add missing reset-names for Tegra HS UART
arm64: tegra: Remove current-speed for SBSA UART
arm64: tegra: smaug: Remove reg-shift for high-speed UART
arm64: tegra: Remove dmas and dma-names for debug UART
arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano
arm64: tegra: Remove duplicate PCI nodes
arm64: tegra: Sort PCI nodes correctly on Orin
arm64: tegra: Add audio support for IGX Orin
arm64: tegra: Update CPU OPP tables
arm64: tegra: Fix HSUART for Smaug
arm64: tegra: Fix HSUART for Jetson AGX Orin
arm64: tegra: Add missing alias for NVIDIA IGX Orin
...
Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Fix i.MX93 ANATOP 'reg' resource size to avoid overlapping with TMU
memory area.
- Fix RTC interrupt level on imx6qdl-phytec-mira board.
- Remove LDB endpoint from from the common imx6sx.dtsi as it causes
regression for boards that has the LCDIF connected directly to
a parallel display.
- Drop CSI1 PHY reference clock configuration from i.MX8MM/N device tree
to avoid overclocking.
- Set a proper default tuning step for i.MX6SX and i.MX7D uSDHC to fix
a tuning failure seen with some SD cards.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmTTYzIUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM5THQf/bDZP+YPT8RxUdxVdL6jT2GGHR3t8
wq3+vM1KVgg+1E9nMBcG0aT1fUTvPM22N5Ae72bGYd69HGbqS64UJ37JlvrSXfwW
QtJHPb9mbDPsdyoLbWBuJq3bdY6NgdbzeKEEGRWlZAkJqvB5a1S63g3riJO89inp
mMsm0dFGn7IZFkhflMtMFL9T0FOz4IwbJGBCm5WvRCR/5nH82MJe5w9JfWBGoRPY
Y0+vm8bS8A/hjQrYVWyAxe1sRAjxNNPWEsjelY/F89gpqOcuBrTTFVmMhEVKX6sd
BjgCQFFWzds4ezmTNloMTyB4dSnW/q2Nsg87A9MXVECW6eIzAeO9p2dINA==
=pxhp
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmTXPu4ACgkQYKtH/8kJ
UieZnRAAnbxsC6/NT7qOwo/d6+hfX2Nh7Tgy9MDLBwIGtzdR822SD0WKwYRIb0K/
iMQMt+6ItPcYDKOLUXKv1MY3QX3BcirvE4yDyPGVxgcnkmL1egeUlYJ4R2U8QnOq
Vwn+cqAcA6RSQIYEV0w32gXHjeDBMdsToT+DlV7id5C6QyreQEkSRzrqf0zm1CTF
zNWCXeaaLkTV+j7W4fb3yPhSMhnnfkwmZB3lVVd5K/vwt7x3OQc7WaSQVNPAcGTC
jiWsbW5KF4HbcukUpb16hyxyyJlt94FxrqqUyN86mj/ONBS55Hf7ilgZX4x/KphG
PJ2V7fnCDnrhIWVEUlknMxLZmPUXTMqaSVsXrx0JOOz+y3KSq6lZudswXPK5fvbV
WGZw9YpC/Hm3hN7Xi+BBUZVJGB7r9pyjcZUcUZBqK1EOxDSRiDMogyC55cC6C6Z2
uX4AfntpeDskj1nUtAgXK38bM1NLQ/jQnkZPVV69qpSkRQK/zLBwNuTSDUtW42vM
ftbbSIyN4tEBQD5bmXy01ug7qxFJaeRQ9dW44UH03zYvDlH5QTrRM64tmySKIRZ+
urab1ShoN0UNA7t9PFpj45bbLb9sndeI6EOh0Vi8RozQ+dCEq1I6HFt54K886qar
sjcsnrJxMZysZnoGGf3q1REe3NjuQ1gRd2nwg4Rbj7VkytuInWI=
=3ZEY
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 6.5, 2nd round:
- Fix i.MX93 ANATOP 'reg' resource size to avoid overlapping with TMU
memory area.
- Fix RTC interrupt level on imx6qdl-phytec-mira board.
- Remove LDB endpoint from from the common imx6sx.dtsi as it causes
regression for boards that has the LCDIF connected directly to
a parallel display.
- Drop CSI1 PHY reference clock configuration from i.MX8MM/N device tree
to avoid overclocking.
- Set a proper default tuning step for i.MX6SX and i.MX7D uSDHC to fix
a tuning failure seen with some SD cards.
* tag 'imx-fixes-6.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx93: Fix anatop node size
ARM: dts: imx: Set default tuning step for imx6sx usdhc
arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration
arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
ARM: dts: imx: Set default tuning step for imx7d usdhc
ARM: dts: imx6: phytec: fix RTC interrupt level
ARM: dts: imx6sx: Remove LDB endpoint
Link: https://lore.kernel.org/r/20230809100034.GS151430@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It's not a valid binding. Instead move the sdio_rst line to the power
sequence and use w_disable1 as the vmmc-supply bringing it more in line
with other SDIO M2 cards.
Resolves following warning:
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dtb: mmc@30b50000: Unevaluated properties are not allowed ('power-supply' was unexpected)
from schema $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
Reported-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Otherwise the A53 cores are shut down which doesn't end well.
Reported-by: David Heidelberg <david@ixit.cz>
Tested-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add basic support for the AM62P5 SK with UART console and
ramdisk as rootfs.
Schematics is at https://www.ti.com/lit/zip/sprr487
Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230811184432.732215-4-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The AM62Px is an extension of the existing Sitara AM62x low-cost family
of application processors built for Automotive and Linux Application
development. Scalable Arm Cortex-A53 performance and embedded features,
such as: multi high-definition display support, 3D-graphics
acceleration, 4K video acceleration, and extensive peripherals make the
AM62Px well-suited for a broad range of automation and industrial
application, including automotive digital instrumentation, automotive
displays, industrial HMI, and more.
Some highlights of AM62P SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Dual/Single core variants are provided in the same package to allow HW
compatible designs.
* One Device manager Cortext-R5F for system power and resource
management, and one Cortex-R5F for Functional Safety or
general-purpose usage.
* One 3D GPU up to 50 GLFOPS
* H.264/H.265 Video Encode/Decode.
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
boot, debug security and crypto acceleration and trusted execution
environment.
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
enabling battery powered system design.
For those interested, more details about this SoC can be found in the
Technical Reference Manual here:
https://www.ti.com/lit/pdf/spruj83
Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230811184432.732215-3-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.
wkup_i2c0, mcu_uart0, main_uart8, main_sdhci0 and main_sdhci1 are required
for bootloader operation on TI K3 AM69-SK EVM. These IPs along with
pinmuxes need to be marked for all bootloader phases, hence add bootph-all
to these nodes in kernel dts.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230811192030.3480616-4-a-nandan@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.
wkup_i2c0, mcu_uart0, main_uart8, fss, ospi0, ospi1, main_sdhci0 and
main_sdhci1 are required for bootloader operation on TI K3 J784S4 EVM.
These IPs along with pinmuxes need to be marked for all bootloader phases,
hence add bootph-all to these nodes in kernel dts.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230811192030.3480616-3-a-nandan@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.
On TI K3 J784S4 SoC, only secure_proxy_mcu and secure_proxy_sa3 nodes are
exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are
used by later boot stages also.
And secure_proxy_mcu and secure_proxy_sa3 are disabled in kernel device
tree, and will be only enabled in R5 bootloader device tree.
So, bootph-pre-ram for secure_proxy_mcu and secure_proxy_sa3 will be
added in R5 bootloader device tree only.
Add bootph-all for all other nodes that are used in the bootloader on
K3 J784S4 SoC, and bootph-pre-ram is not needed specifically for any node
in kernel dts.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230811192030.3480616-2-a-nandan@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable CONFIG_DRM_ITE_IT66121.
ILITEK ITE-IT66121 is an HDMI transmitter, which takes parallel video
signals (DPI) as input. It is being used on TI's AM625 SoC based
BeaglePlay platform[0].
[0]: https://beagleboard.org/play
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-7-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The DSS outputs DPI signals via its second video port (VP2). The DPI
output from DSS is 24 bits (RGB888) and is forwarded to an HDMI
transmitter (ITE-IT66121) on the BeaglePlay platform. For audio output,
BeaglePlay uses mcasp1.
Add pinmux info for DSS DPI signals.
Further, add support for HDMI audio and video output.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-6-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable audio output over HDMI instead of the 3.5mm jack.
A FET switch (U65) on the EVM muxes serial audio lines coming from McASP
between the codec (tlv320aic3106) and the HDMI bridge (sii9022).
By default it uses the codec, but it can be toggled to use the HDMI
bridge by shorting a (J24) header on the board.
Signed-off-by: Jai Luthra <j-luthra@ti.com>
[a-bhatia1: Cosmetic changes]
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-5-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The DSS outputs DPI signals via its second video port (VP2). The DPI
output from DSS is 24 bits (RGB888) and is forwarded to an HDMI
transmitter (SIL9022) on the board.
Add pinmux info for DSS DPI output.
Add DT nodes for SIL9022 HDMI transmitter (TX), and the HDMI connector
on the AM625 SK and AM62-LP SK platforms.
Additionally, connect the output of DSS (VP2) with input of the HDMI TX,
and the output of HDMI TX to the input of the HDMI connector.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-4-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Display SubSystem (DSS) DT node for the AM625 SoC.
The DSS supports one each of video pipeline (vid) and video-lite
pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and
DPI signals on another (VP2). The video ports are connected to the
pipelines via 2 identical overlay managers (ovr1 and ovr2).
Also add the DT node for DSS clock divider. This is a fixed-factor-clock
and does not have any register. This comes into effect whenenver OLDI
display is used. The input to this divider is a serial clock used by
OLDI TXes. The divider divides the input clock by 7, and provides the
pixel clock to VP1.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-3-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
The Display Data Channel (DDC) transactions between an HDMI transmitter
(SIL9022A in this case) and an HDMI monitor, occur at a maximum of
100KHz. That's the maximum supported frequency within DDC standards.
While the SIL9022A can transact with the core at 400KHz, it needs to
drop the frequency to 100KHz when communicating with the monitor,
otherwise, the i2c controller times out and shows warning like this.
[ 985.773431] omap_i2c 20010000.i2c: controller timed out
That feature, however, has not been enabled in the SIL9022 driver.
Since, dropping the frequency doesn't affect any other devices on the
bus, drop the main-i2c1 frequency from 400KHz to 100KHz.
Fixes: a841581451af ("arm64: dts: ti: Refractor AM625 SK dts")
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20230809084559.17322-2-a-bhatia1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Add initial device tree support for the Qualcomm IPQ5018 SoC and
rdp432-c2 board.
Few things like 'reboot' does not work because, couple of more 'SCM'
APIS are needed to clear some TrustZone settings. Those will be
posted separately.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the second MAC on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Once we add a second ethernet node, the MDIO bus names will conflict
unless we provide aliases. Add one for the existing ethernet node.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
For improved readability order the aliases alphabetically for
sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index
the first one for better readability.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
