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for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
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Merge tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
* tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Add reference to RPi 3 A+
ARM: dts: add Raspberry Pi 3 A+
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
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Merge tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards are the Rock Pi 4, NanoPC-T4 and NanoPi-M4, with the last
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
* tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: clean up the abuse of disable-wp
arm64: dts: rockchip: 'Fix' nanopi4 uSD card detect
arm64: dts: rockchip: Add NanoPC-T4 IR receiver
arm64: dts: rockchip: Refine nanopi4 differences
arm64: dts: rockchip: Add DT for NanoPi M4
arm64: dts: rockchip: add ROCK Pi 4 DTS support
arm64: dts: rockchip: Add devicetree for NanoPC-T4
arm64: dts: rockchip: enable analog audio node for rock64
arm64: dts: rockchip: move rk3328 #sound-dai-cells to the soc dtsi
arm64: dts: rockchip: add rk3328 ACODEC node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
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Merge tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.0, 3rd round:
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
* tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: Fix boot from eMMC
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Merge tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fix for new dtc graph warnings and a regulator fix for rock64.
* tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: enable usb-host regulators at boot on rk3328-rock64
arm64: dts: rockchip: fix graph_port warning on rk3399 bob kevin and excavator
This patch is a port of the fix from
commit 73e42e186699 ("arm64: dts: rockchip: fix rock64 gmac2io stability
issues")
As per that patch, enabling thresh dma mode force disables checksuming.
This is necessary as tx checksuming does not work with packets larger
than 1498.
The rk3328-roc-cc board exhibits tx stability issues with large packets
similar to rock64's issues. This patch resolves that issue.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
vcc5v0_host and vcc5v0_typec is supplied by vcc5v0_usb and not vcc5v0_sys.
add node for vcc5v0_usb fixed regulator.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
lcd panel pinmux is unused and the pin actually for something different,
so removing it.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rename dc12, vcc_sys, vcc1v8_pmu regulators and make it more redable as per the
schematic of rk3399-rockpro64.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Describe the Bluetooth portion of the Ampak combo module - this is
either an AP6356S or an AP6212 depending on the board variant, but
there are no relevant compatibility differences between the two.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for
the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Adds support for USB0 and USB1 instances on the AM6 SoC.
USB0 is limited to high-speed for now.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main System control module support is added to the device tree to allow
driver to access to their control module registers.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf0000 for SYSFW
- Upper 1MB for cache
The reserved locations are subject to change at runtime by
the bootloader.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Sort the labels in the same order as in the corresponding dtsi file,
in other words, the order of reg address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The peripheral bus on the i.MX8MQ is still limited to 32bits, so
we need to declare the usable range for device DMA operations, as
the DRAM will extend across the 32bit boundary if more than 3GB
are installed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add RTC support for i.MX8MQ.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Chris Spencer <christopher.spencer@sea.co.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable the Freescale/NXP QuadSPI controller with a proper pinctrl set on
the i.MX8MQ EVK board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
memory range to accommodate the QuadSPI-memory region.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the three ECSPI ports present on i.MX8MQ.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add devicetree support for Sophon Edge board from Bitmain based on
BM1880 SoC. This board is one of the 96Boards Consumer and AI platform.
More information about this board can be found in 96Boards product page:
https://www.96boards.org/documentation/consumer/sophon-edge/
Only UART peripheral support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reference the PHY nodes from the USB controller nodes.
The USB3 host controller is wired to:
* the first PHY of the COMPHY IP
* the OTG-capable UTMI PHY
The USB2 host controller is wired to:
* the host-only UTMI PHY
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The SATA node is wired to the third PHY of the COMPHY IP.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The PCIe node is wired to the second PHY of the COMPHY IP.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Describe the A3700 COMPHY node. It has three PHYs that can be
configured as follow:
* PCIe or GbE
* USB3 or GbE
* SATA or USB3
Each of them has its own memory area.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
By using the new binding for the partitions for the flashes we don't need
anymore to use #size-cells and #address-cells at the flash node level.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The mv88e6341 ethernet switch needs the cpu port control register to be
set with TX and RX internal delay in order to work.
This fixes ethernet support on system booted via a bootloader that
has not already configured this register (e.g. mainline u-boot, or
vendor u-boot compiled without ethernet support).
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
In order to be able to communicate with the 88e6341 switch some pins
have to be repurposed as RGMII and SMI pins.
This fixes ethernet support on system booted via a bootloader that
has not already configured those pins (e.g. mainline u-boot, or vendor
u-boot compiled without ethernet support).
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add the G12a (S905X2) based X96 Max board[1].
There is no branding for the manufacturer anywhere on the product, so it
took some digging[2] to find the manufacturer. But since there's
nothing about the maker on the product I've left it out of the DT name
because 1) nobody will know that name and 2) keeps the DT filename
shorter.
[1] https://www.cnx-software.com/2018/09/25/x96-max-amlogic-s905x2-tv-box/
[2] https://fccid.io/2AI6D-X96MAX
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the peripheral clock controller to the g12a SoC DT
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds initial support for micro-DPU (uDPU) board which is based on
Armada-3720 SoC. micro-DPU is the single-port FTTdp distribution point
unit made by Methode Electronics which offers complete modularity with
replaceable SFP modules both for uplink and downlink (G.hn over
twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable).
On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Luis Torres <luis.torres@methode.com>
Cc: Scott Roberts <scott.roberts@telus.com>
Cc: Paul Arola <paul.arola@telus.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch enables PCIEC0 PCI express controller on the sub board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
mapping for pciec0 node. Also declare pcie bus clock, since it is
generated on the CAT874 main board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch define OOP tables for all CPUs.
This allows CPUFreq to function.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Successfully tested on H3 ES2.0 and M3-N ES1.0.
Transfer rates where >160MB/s for H3 and >200MB/s for M3-N.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When commit 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module
device node") was posted upstream no clocks were specified. However,
when the pack was picked into the Chrome OS kernel tree (allegedly
directly from the mailing list post) it had clock properties.
I presume that the clock should be there, so let's add it.
Fixes: 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node")
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
[bjorn: Add also the required iommus property]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the clock measure device to the g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the clock measure device to the axg SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
