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4 Commits

Author SHA1 Message Date
Boris Brezillon
377e517b5f mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg 
NAND datasheets usually give the maximum number of bad blocks per LUN
and this number can be used to help upper layers decide how much blocks
they should reserve for bad block handling.

Add a max_bad_eraseblocks_per_lun to the nand_memory_organization
struct and update the NAND_MEMORG() macro (and its users) accordingly.

We also provide a default mtd->_max_bad_blocks() implementation.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
 2019-04-08 10:21:08 +02:00
Emil Lenngren
f4cb4d7b46 mtd: spinand: macronix: Fix ECC Status Read 
The datasheet specifies the upper four bits are reserved.
Testing on real hardware shows that these bits can indeed be nonzero.

Signed-off-by: Emil Lenngren <emil.lenngren@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
 2019-02-05 15:39:39 +01:00
Miquel Raynal
3dfa025f89 mtd: spinand: macronix: Add support for MX35LF2GE4AB 
MX35LF2GE4AB is almost identical to MX35LF1GE4AB except it has 2 times
more eraseblocks per LUN and exposes 2 planes instead of 1.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
 2018-07-18 09:24:12 +02:00
Boris Brezillon
b02308af05 mtd: spinand: Add initial support for the MX35LF1GE4AB chip 
Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
 2018-07-18 09:24:12 +02:00