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Similarly to what was earlier done for other Nyan variants, move the eDP
panel on the FHD models to the AUX bus as well.
Suggested-by: Dmitry Osipenko <digetx@gmail.com>
Fixes: ef6fb9875ce0 ("ARM: tegra: Add device-tree for 1080p version of Nyan Big")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move the eDP panel on Venice 2 and Nyan boards into the corresponding
AUX bus device tree node. This allows us to avoid a nasty circular
dependency that would otherwise be created between the DPAUX and panel
nodes via the DDC/I2C phandle.
Fixes: eb481f9ac95c ("ARM: tegra: add Acer Chromebook 13 device tree")
Fixes: 59fe02cb079f ("ARM: tegra: Add DTS for the nyan-blaze board")
Fixes: 40e231c770a4 ("ARM: tegra: Enable eDP for Venice2")
Signed-off-by: Thierry Reding <treding@nvidia.com>
The properties have been commented out to prevent a regression a while
ago. The first regression should be resolved by commit 44af7927316e
("spi: Map SPI OF client IRQ at probe time").
The second regression is probably addressed by commit 494fd7b7ad10
("PM / core: fix deferred probe breaking suspend resume order") and/or
maybe others. Readd the gpio-ranges properties to see whether
regressions still get reported.
This reverts commit 4f1d841475e1 ("ARM: tegra: Comment out gpio-ranges
properties").
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Tested-by: Agneli <poczt@protonmail.ch>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable S/PDIF controller to enable HDMI audio support on Acer A500.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS
Transformer tablets.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Make Nexus 7 device-tree to use common LVDS bridge description. This makes
device-trees more consistent.
[digetx@gmail.com: factored Nexus7 change into separate patch and wrote commit message]
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
CPU of Nyan Chromebooks is overheating badly because apparently hardware
soctherm controller doesn't work well. Add CPU thermal zones to enable
software thermal control over CPU and fix the overheat trouble.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due
to Linux kernel CPUFreq driver which didn't support suspend-resume. That
problem was fixed years ago, but DFLL was never re-enabled.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable HDMI CEC on Nyan Chromebooks. It allows to control TV over HDMI.
Suggested-by: Thomas Graichen <thomas.graichen@gmail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
If an USB port is an OTG port, then we should add the usb-role-switch
property. Otherwise XUSB setup fails and therefore padctl is unable to
set up the ports. This leads to broken USB and PCIe ports. Add the
usb-role-switch properties to Tegra124 device-trees to fix the problem.
The error message shown without this patch is e.g:
usb2-0: usb-role-switch not found for otg mode
[digetx@gmail.com: improved commit message]
Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add dedicated device-tree for 1080p version of Nyan Big in order to
describe display panel properly. FHD panel doesn't support modes other
than 1080p, hence it's wrong to use incompatible lower resolution panel
in device-tree.
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add device-tree for ASUS Transformer Pad TF300TG, which is a NVIDIA
Tegra30-based 2-in-1 detachable, originally running Android. It's a
variant of the TF300T that has a 3G modem.
Link: https://wiki.postmarketos.org/wiki/ASUS_Transformer_Pad_(asus-tf300t)
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: cosmetic fixups]
Signed-off-by: Thierry Reding <treding@nvidia.com>
All Tegra30 ASUS tablets have a similar design pattern in terms of
hardware integration of LVDS display panels, like exactly the same GPIOs
are used for power and reset, etc. Add a common device-tree for LVDS
display panels of Tegra30 ASUS tablets to avoid replicating the
boilerplate panel description.
[digetx@gmail.com: factored out common part into separate patch and wrote commit message]
Co-developed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add common DTSI for Tegra30 ASUS Transformers. It will be used by multiple
device-trees of ASUS devices. The common part initially was born out of
the ASUS TF300T tablet's device-tree that was created by Michał Mirosław.
It was heavily reworked and improved by Svyatoslav Ryhel, Maxim Schwalm,
Ion Agorria et al.
[digetx@gmail.com: factored out common part into separate patch and wrote commit message]
Co-developed-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Ion Agorria <ion@agorria.com>
Co-developed-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Co-developed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: cosmetic fixups]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move the default state pinmux definition into the pinmux node. There's
no need for the indirection via the phandle.
Note that the phandle indirection is kept for the EMC operating
performance point tables because they reference nodes that are defined
in an external file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Use the correct "reset-gpios" property for the I2C mux reset GPIO
reference instead of the deprecated "reset-gpio" property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SLINK controller found on Tegra30 is not compatible with its
predecessor found on Tegra20. Drop the fallback compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Ouya board specifies the #reset-cells property for the GPIO
controller. Since the GPIO controller doesn't provide reset controls
this is not needed, so they can be dropped.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The clock-frequency property was never used and is deprecated now.
Remove it from Nexus 7 device-tree.
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The +V1.2_VDD_CORE regulator on Apalis and Colibri boards uses the
unsupported ti,vsel{0,1}-state-low properties. It turns out that these
are in fact the default and can be overridden by ti,vsel{0,1}-state-high
properties if needed. Drop them since they are not needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Medcom Wide and PAZ00 boards don't specify the power supply for the
backlight, which means that the Linux driver will provide a dummy one.
Wire up an explicit dummy to also make the DT schema validation succeed.
Unfortunately I don't have access to the schematics for the Medcom Wide,
so I don't know if a more accurate description is possible.
The AC100 (PAZ00) schematics from here:
https://www.s-manuals.com/pdf/motherboard/compal/compal_la-6352p_r1.0a_schematics.pdf
aren't entirely clear which one of the supplies powers backlight, but
the panel supply is probably close enough.
Based on work by David Heidelberg <david@ixit.cz>.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PHY reset GPIO references belong in the USB PHY nodes, where they
already exist. There is no need to keep them in the USB controller's
device tree node as well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The device tree node for the built-in ASIX Ethernet device on Colibri
boards needs a compatible string in order to pass DT schema validation.
Add the USB VID,PID compatible string as required by the DT schema for
USB devices.
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The "pwm-" prefix currently matches the DT schema for PWM controllers
and throws an error in that case. This is something that should be fixed
in the PWM DT schema, but in this case we can also preempt any such
conflict by naming the nodes after the pins like we do for many others
of these nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra124, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement. Reorganize CPU and EMC OPP table device-tree nodes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When the Tegra High-Speed UART is used instead of the regular UART, the
reg-shift property is implied from the compatible string and should not
be explicitly listed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to be able to pass DT schema validation, change the GPU nodes'
unit-address to the standard notation. Previously this was using a "0,"
prefix that originated from a time when the top-level device tree node
contained #address-cells = <2>.
Note that this technically breaks backwards-compatibility with certain
older versions of the U-Boot bootloader because early versions used a
hard-coded DT path lookup to find the GPU node and perform some fixups
on it. However, this was changed to a compatible string based lookup in
April 2016, so it's reasonable to expect people to update U-Boot on the
systems that they want to use this updated kernel DTB with.
Signed-off-by: Thierry Reding <treding@nvidia.com>
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.
Signed-off-by: Thierry Reding <treding@nvidia.com>
