IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
Record the address of the mcount call-site. Currently all archs except sparc64
record the address of the instruction following the mcount call-site. Some
general cleanups are entailed. Storing mcount addresses in rec->ip enables
looking them up in the kprobe hash table later on to check if they're kprobe'd.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Cc: davem@davemloft.net
Cc: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either
be used in x4 mode or in quad x1 mode. This patch adds an accessor
function to the generic plat-orion PCIe handling code to detect in
which of the two modes we're running (which is determined by strap
pins and/or configured by the bootloader).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.
Note that:
- Page table walks are outer uncacheable on Kirkwood and Discovery
Duo, since the ARMv5 spec provides no way to indicate outer
cacheability of page table walks (specifying it in TTBR[4:3] is
an ARMv6+ feature).
This requires adding L2 cache clean instructions to
proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled
by defining a new TLB type (TLB_FEROCEON) which is almost identical
to the v4wbi one but provides a TLB_L2CLEAN_FR flag.
- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
range by MVA' and 'invalidate L2 range by MVA') operations, and this
patch uses those range operations for all Linux outer cache
operations, as they are faster than the regular per-line operations.
L2 range operations are not interruptible on this hardware, which
avoids potential livelock issues, but can be bad for interrupt
latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
allows you to select the maximum range size to operate on at once.
(Valid range is between one cache line and one 4KiB page, and must
be a multiple of the line size.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.
This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This define isn't used anywhere in the kernel tree -- nuke it.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>
The implementation for memory copy functions on ARM had a (disabled)
provision for aligning the source pointer before loading registers with
data. Turns out that aligning the _destination_ pointer is much more
useful, as the read side is already sufficiently helped with the use of
preload.
So this changes the definition of the CALGN() macro to target the
destination pointer instead, and turns it on for Feroceon processors
where the gain is very noticeable.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This adds the definition for the third USB port control register UP3OCR. It is
used on the EZX GSM mobile phones.
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Macros like Fld() or FShft used in regs-lcd.h are defined in bitfield.h, but
the latter is not included.
Also fix one whitespace issue while being there.
Signed-off-by: Antonio Ospite <ao2@openezx.org>
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is basically s/at91_nand/atmel_nand/g with some manual inspection.
Signed-off-by: Håvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The AT91 NAND driver needs just a few tiny modifications to work on
AVR32 as well. Rename it atmel_nand to reflect this.
Also move the ECC register definitions into drivers/mtd/nand since they
are only useful to the atmel_nand driver, and get rid of the useless
filename at the top of each file.
Signed-off-by: Håvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The power manager and core clock registers aren't present in PXA3
CPUs. Move them out of pxa-regs.h into pxa2xx-regs.h, and include
pxa2xx-regs.h where necessary.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adds support for the USB High Speed Device Port on the AT91SAM9RL
system on chip. The AT91SAM9RL uses the same UDPHS IP as the AVR32 and
the AT91CAP9 (atmel_usba_udc driver).
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is patch 2 of 2 adding support for the USB High Speed Device Port
on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP
as the AVR32 and the AT91SAM9RL.
This patch declares the UDPHS ressources in the at91cap9 (cpu and
adk board) files, wires up the atmel_usba_udc driver to them,
and activates the driver in the defconfig.
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is patch 1 of 2 adding support for the USB High Speed Device Port
on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP
as the AVR32 and the AT91SAM9RL.
This patch makes the generic AT91 adaptations, mainly dealing with
the addition of the UDPHS UTMI clock.
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add support for three AT91-based boards available from Calao Systems:
USB_A9260, USB_A9263 and QIL_A9260.
Signed-off-by: Grégory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The current __raw_write_can_lock macro tests whether the lock can be
locked by checking if it is equal to 0x80000000, whereas the lock
should be lockable if its value is 0 i.e. unlocked state is
represented by 0. Hence the macro should test the value of lock
against 0 and not 0x80000000.
Signed-off-by: Surinder Pal Singh <srplsnh@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PSKTSEL can be routed to GPIO pin 104. This configuration is used by
HP iPAQ hx4700.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Jrgen Schindele <linux@schindele.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some additional alternate gpio definitions relating
to FFUART and USB on the pxa27x. These are used on
the xbow imote2 platform.
Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Follow suit from kprobe implementations on other archs and make kretprobe_trampoline non-static. Ftrace implmentation (more specifically, kernel/trace/trace.c) requires access to it (see-> http://kerneltrap.org/mailarchive/linux-kernel/2008/5/27/1955234).
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
AT91 has one include loop in its header files:
include/asm-arm/io.h <- include/asm-arm/arch-at91/io.h <-
include/asm-arm/io.h
Circular include dependencies are dangerous since they can result in
inconsistent definitions being provided to other code, especially if
'#ifndef' constructs are used.
Solve this by removing the offending includes. Built tested using my
AT91 configuration.
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It's not very critical because __REG2 isn't used in assembler code
currently.
Additionally some white space noise is fixed.
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
atags.c was the only user of KEXEC_BOOT_PARAMS_SIZE and kexec.h
was only included to get that definition.
Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Acked-by: Uli Luckas <u.luckas@road.de>
OMAP has two include loops in its header files:
asm-arm/hardware.h <- asm-arm/arch-omap/io.h <-
asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h
asm-arm/arch-omap/board-palmte.h <-
asm-arm/arch-omap/hardware.h <- asm-arm/hardware.h <-
asm-arm/arch-omap/gpio.h <- asm-arm/arch-omap/board-palmte.h
Circular include dependencies are dangerous since they can result in
inconsistent definitions being provided to other code, especially if
'#ifndef' constructs are used.
Solve these by removing the offending includes, and add additional
includes where necessary.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
For the simple read_cpuid() macro case the variable processor_id has
no definition on use of the macro. Add an extern for it. Move all the
processor ID macros into the #ifndef __ASSEMBLEY__ block.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The non-MMU case also needs the type definition of pgtable_t.
So move it out of a CONFIG_MMU conditional section.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/plat-omap/clock.c:397: warning: "struct cpufreq_frequency_table" declared inside parameter list
arch/arm/plat-omap/clock.c:397: warning: its scope is only this definition or declaration, which is probably not what you want
arch/arm/plat-omap/clock.c: In function `clk_init_cpufreq_table':
arch/arm/plat-omap/clock.c:402: error: structure has no member named `clk_init_cpufreq_table'
arch/arm/plat-omap/clock.c:403: error: structure has no member named `clk_init_cpufreq_table'
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that all drivers using it are gone, remove the old ARM RTC library.
Acked-by: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
collie.h:
* add some meaningfull names to some gpios
collie.c:
* initialize cpu registers correctly
Signed-off-by: Thomas Kunze <thommycheck@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The PXA25x and PXA27x USB device controller register definitions are
different. Currently, they live side by side in pxa-regs.h, but only
one set is available depending on the setting of PXA25x or PXA27x.
This means that if we build to support both PXA25x and PXA27x, the
PXA27x definitions are unavailable, even to PXA27x specific code.
Remove these definitions from pxa-regs.h, and place them in separate
files. Include these files where appropriate.
Note: according to the dependencies in drivers/usb/gadget/Kconfig,
we do not support the UDC on PXA27x nor PXA3xx CPUs, so remove the
platform devices from pxa27x.c and pxa3xx.c.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Parenthesis fix in include/asm-arm/arch-omap/control.h
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
irqs.h:
* rename IRQ_LOCOMO_SPI_OVRN to IRQ_LOCOMO_SPI_REND
locomo.h:
* add some definition for locomo spi controller
* correct some errors
locomo.c:
* correct some errors
* add set_type for locomo gpio irq chip
Signed-off-by: Thomas Kunze <thommycheck@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
dyntick is superseded by the clocksource/clockevent infrastructure,
using the NO_HZ configuration option. No one implements dyntick on
ARM anymore, so it's pointless keeping it around. Remove dyntick
support.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the omap2_set_globals_{242x,243x,343x}() functions. These
functions are called early upon boot in the map_io() functions in the
board-specific init files.
This patch was accidentally left out of the earlier series.
This fixes omap2 booting as noted by Kyungmin Park <kmpark@infradead.org>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kyungmin Park <kmpark@infradead.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Related to d3930614e68bdf83a120d904c039a64e9f75dba1.
RCSR is only present on PXA2xx CPUs, not on PXA3xx CPUs. Therefore,
we should not be unconditionally writing to RCSR from generic code.
Since we now clear the RCSR status from the SoC specific PXA PM code
and before reset in the arch_reset() function, the duplication in
the corgi, poodle, spitz and tosa code can be removed.
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Each time a pxa type cpu went in suspend, a portion of
kmalloc memory was corrupted.
The issue was an incorrect length allocation introduced by
the commit 711be5ccfe9a02ba560aa918a008c31ea4760163 for
the save registers array (=> overflow).
Signed-off-by: Robert Jarzmik <rjarzmik@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This modifies <asm-arm/types.h> to use the <asm-generic/int-*.h>
generic include files.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Ben Dooks <ben-linux@fluff.org>
