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5 Commits

Author SHA1 Message Date
Ley Foon Tan
8e3d7c834b nios2: fix cache coherency 
There is intermittent cache coherency issue caught in toolchian tests.
Revert to use flushd.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
 2015-11-26 22:25:58 +08:00
Ley Foon Tan
1a70db49a7 nios2: rework cache 
- flush dcache before flush instruction cache
- remork update_mmu_cache and flush_dcache_page
- add shmparam.h

Signed-off-by: Ley Foon Tan <lftan@altera.com>
 2015-04-24 14:49:53 +08:00
Ley Foon Tan
170c381f6b nios2: remove end address checking for initda 
Remove the end address checking for initda function. We need to invalidate
each address line for initda instruction, from start to end address.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
 2015-04-20 10:52:06 +08:00
Ley Foon Tan
4a89c3088f nios2: fix cache coherency issue when debug with gdb 
Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.

Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.


Signed-off-by: Ley Foon Tan <lftan@altera.com>
 2015-04-10 11:10:08 +08:00
Ley Foon Tan
93c91cb228 nios2: Cache handling 
This patch adds functionality required for cache maintenance.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
 2014-12-08 12:55:54 +08:00