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The hardware does not have support for ATIM processing, and the driver
does not set up ah->atim_window anywhere. Additionally, the code can
clobber the timer used by P2P powersave.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
- Use generic bitops instead of custom hackery
- Move interrupt enable/disable logic from ath9k to ath9k_hw
- Decouple ISR call from btcoex
- Make the overflow callback optional (to prevent IRQ storms)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
TSF accuracy is not needed here, and there is only one usable generic
timer that is supported by all chips and uses the primary TSF counter.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
There's no need to truncate curchan->hw_value to u8
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Move ath9k_hw_set_rfmode() after ath9k_hw_process_ini() in order to avoid
AR_PHY_MODE register is overwritten with default values by
ar9003_hw_process_ini()
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
On suspend/resume, firmware will restart and gpios
configuration will be reseted. Restore this
configureation at least for LEDs
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Initialize first chain flags in ath9k_build_tx99_skb() according to
configured channel mode and channel width
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The internal regulator needs to be programmed
correctly for AR955x.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Adjusting the CCA registers for maximum permissible
noise floor in ETSI/Japan domains has to be done for
all AR9003 family chips.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Now that the Buffalo-specific initvals have been
moved to a separate array, update the default high
power TX gain table for all AR9300 v2.2 devices.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The Buffalo device WZR-HP-G450H uses the index 3 for TX gain,
which is set to the high_power table currently. Later variants
of the router use the same index, but instead refer to the
low_ob_db gain table. This is not handled in the driver since
there is no way to distinguish board revisions and the high_power
table is used (incorrectly) for the newer variants.
By default, devices based on AR9300 using the TX gain index 3 have
to use the high_power table. To make sure that WZR-HP-G450H is not
broken when the high_power table is updated, use a separate array
based on information obtained from the platform data.
The current situation where only the original variant of WZR-HP-G450H
works properly stays unchanged.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
* Update radio/baseband/gain tables.
* Mark ar9331_modes_high_power_tx_gain_1p1 as a duplicate
* ar9331_1p1_mac_postamble is not a duplicate.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Enable the ALWAYS_KEYSEARCH bit in the initvals. Currently
this is done in the driver, but adding this to the initvals
makes it easier to be in sync with the INI files given
by the systems engineering team.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Certain baseband registers require different values
to be programmed when operating in a DFS channel to
ensure that radar detection works correctly. This
is required for AR9300, AR9340 and AR9580.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Initialize first chain attempt counter to 1 in ath9k_build_tx99_skb().
Otherwise multi-retry chain is initialized to {idx,count} = {-1, 0} in
rate_control_fill_sta_table() and tx99 transmission rate is not configured in
rate_control_apply_mask() since first chain idx is set to -1
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This is missing for AR9300, AR9580 and AR9340.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
* Baseband updates
* Remove ar9340Common_rx_gain_table_1p0 since it is a duplicate.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The initvals for AR9462 v2.1 are very similar to v2.0.
Identify duplicate arrays and reuse the values from v2.0
to reduce module size.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The initialization arrays for v1.1 AR9565
are mostly the same as v1.0/v1.0.1 except for
radio_postamble.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Since IQ calibration is done as part of AGC calibration for
AR9485 and above, remove the seperate IQ calibration code.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The CHANNEL_HT flag is insignificant for fast channel change conditions,
since it does not affect any important part of the hardware reset /
channel setup.
Scanning usually runs with HT disabled, so this change will slightly
improve scan time on many chipsets.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
A cold reset can be triggered because of DMA stop issues, and this leads
to TSF being cleared on all chipsets. To properly deal with this, always
save the TSF.
Additionally, account for the time it takes to do the actual chip reset,
which can be quite significant. On AR9344 it takes around 4.5 ms.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Instead of checking the queues in a loop with hardcoded sleep times
inbetween, use a wait queue to trigger queue checks after the tx
processing tasklet has run.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
If the software has processed all packets, checking the hardware queue
is unnecessary.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
When operating in client mode, the short period of time between scanning
and associating is often enough to put the hardware through several
FULL-SLEEP <-> AWAKE transitions, each wakeup requiring a reset to fully
recover the hardware.
This is completely unnecessary and can easily be avoided by deferring
the switch to full sleep.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Since calibration data reuse is not enabled in
SoC chips, simplify the IQ calibration code.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
CL calibration is applicable for all chips and the
enable/disable knob comes via the INI file. For PCOEM
chips, the calibration data is reused when Fast Channel Change
is used. Caldata reuse is not enabled for SoC chips, so remove
the CL post processing code.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
TX IQ calibration is always enabled for SoC chips.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
RTT is enabled only for AR9462 and MCI for AR9462/AR9565.
Also, manual peak calibration is not done for any of the
SoC chips.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Though there is some overlap between the calibration mechanisms
of PC-OEM cards and SoC chip families, dumping both of them
into a single function makes things hard to understand.
ar9003_hw_init_cal() is unreadable with chip-specific segments
scattered around. To make the logic understandable, use
different functions for client cards and SoC chips. Some
code is duplicated, but in the long run, it makes the code
more maintanable.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
SC_OP_INVALID is zero so the test is always false. We're supposed to be
testing the lowest bit instead.
Fixes: 89f927af7f33 ('ath9k: add TX99 support')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
CUS227, which is an AR9340 based card used in Qualcomm's
Allplay platforms requires a custom TX gain array, based
on the index 7. Add suport for this.
Cc: Michael Larson <mlarson@qce.qualcomm.com>
Cc: Stephen Collmeyer <scollmey@qce.qualcomm.com>
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This HW config option is always set to true and is not needed.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
