IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
sirfsoc_gpio_set_input() is called in those functions which have
held the spinlock, so delete the duplicated locking.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We always use pinctrl_request_gpio() to get GPIO, If we don't have these
missing pins in the pin list, gpio_request and related operations will fail
for them.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adds support for displaying the individual pin h/w config state.
Signed-off-by: Matt Porter <mporter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'pindesc' was not freed when returning from an error induced
exit path.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
From Jason Cooper:
New drivers:
- pinctrl (dove, kirkwood, mvebu)
- gpio (mvebu)
* 'kirkwood/drivers' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: add gpio support in defconfig
arm: mvebu: add DT information for GPIO banks on Armada 370 and XP
arm: mvebu: use GPIO support now that a driver is available
Documentation: add description of DT binding for the gpio-mvebu driver
gpio: introduce gpio-mvebu driver for Marvell SoCs
arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms
arm: mvebu: split Kconfig options for Armada 370 and XP
ARM: mvebu: adjust Armada XP evaluation board DTS
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: Add pinctrl support to Armada XP SoCs
pinctrl: mvebu: add pinctrl driver for Armada XP
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: kirkwood pinctrl driver
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: pinctrl driver core
Signed-off-by: Olof Johansson <olof@lixom.net>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Conflicts:
arch/arm/Kconfig
Because of a typo, incorrect field of a structure was being checked.
This patch fixes the check to use correct field.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Although the function is used only a single time, it is not performance
critical and it is pretty heavy, so let the compiler decide whether to
inline it instead.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Current way of finding the wakeup-eint node scans the whole device tree
not only children of the pinctrl node, so it might detect a wakeup-eint
node of another pinctrl device.
This patch limits the scope of looking for nodes only to subnodes of the
pinctrl node.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The exynos_irq_demux_eint utility function is used in chained IRQ
handler for EINT16-31 to handle multiplexed interrupts. Inlining it
should improve the performance a bit.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
A bit in EINTxx_PEND register is set regardless of interrupt mask, which
causes spurious interrupts. To avoid them, the read value of pending
register must be masked with current interrupt mask manually.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
To mask GPIO/wakeup IRQ, the corresponding bit in mask register has to
be set.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Pins used as GPIO interrupts need to be configured as EINTs. This patch
adds the required configuration code to exynos_gpio_irq_set_type,
to set the pin as EINT when its interrupt trigger is configured.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Now that Tegra's pinmux is configured solely from device tree, there's
no need for the pinconf types to be defined in arch/arm/mach-tegra/.
Move it into the pinctrl directory to clean up mach-tegra, as a pre-
requisite for single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Instead of using a temporary buffer, snprintf() and kstrdup(), just
use kasprintf() that does the same thing in just oneline.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Colin Cross <ccross@google.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
Implement support for pinctrl on lantiq/xway socs. The IO core found on these
socs has the registers for pinctrl, pinconf and gpio mixed up in the same
register range. As the gpio_chip handling is only a few lines, the driver also
implements the gpio functionality. This obseletes the old gpio driver that was
located in the arch/ folder.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
With pinctrl-single,bits it is possible to update just part of the register
within the pinctrl-single,function-mask area.
This is useful when one register configures mmore than one pin's mux.
pinctrl-single,bits takes three parameters:
<reg offset, value, sub-mask>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
[Removed a misplaced comment]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Another possible pin configuration for the MC1 pin group.
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the pcs->fmask to make sure that the value is not changing (setting)
bits in areas where it should not.
To avoid situations like this:
pmx_dummy: pinmux@4a100040 {
compatible = "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x00ff>;
};
&pmx_dummy {
pinctrl-names = "default";
pinctrl-0 = <&board_pins>;
board_pins: pinmux_board_pins {
pinctrl-single,pins = <
0x6c 0xf0f
0x6e 0x10f
0x70 0x23f
0x72 0xa5f
>;
};
};
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.
This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This makes us possible to define pinmux mapping in board-specific DTS.
prima2.dtsi provides all possible (groups,functions) configuration, and
device in .dts select configurations from dtsi files.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The io-pci series has gained a merge to resolve a nontrivial
conflict.
* cleanup/io-pci:
ARM: Fix ioremap() of address zero
Also includes an update to Linux 3.6-rc3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.
Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.
If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.
To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
pinctrl drivers number pad from 1. It causes problem/confusion when
driver accesses imx51_pinctrl_pads array using pin ID as the index.
Change imx51_pads and imx53_pads numbering start from 0.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This is mostly cut'n'paste from the imx51 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx35.h.
Changes since (implicit) v1
- remove references to file names in binding documentation
- remove sed commands from comments in driver
- add explicit numbers for pins and functions
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds support for the STN8815 ASIC for the Nomadik pin
controller.
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is yet another way to mux the keyboard, so fix up that
group.
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSI should be 0x7bc rather
than NO_PAD. This error will cause SD2 probe failure.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In function pinctrl_get_locked, pointer p is returned on
error, and also return on no_error.
So, we just return it with no error test.
It's pretty the same in function pinctrl_lookup_state_locked:
state is returned in every case, so we drop the error test
and just return state.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
The irqdomain conversion failed to notice that we do not always
have a DT node to dereference, fix this up by using a simple
dev_err() that also tells the name of the device.
Cc: Loic Pallardy <loic.pallardy@st.com>
Cc: Patrice Chotard <patrice.chotard@stericsson.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move the platform-specific COH901 pin control header out of the
ARM tree and down into the proper platform data include
directory.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As the non-U335 U300 variants are retired from the ARM tree,
also delete the pinctrl driver codepaths for these variants.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
devm_kfree should not have to be explicitly used.
The semantic patch that fixes this problem is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression x,d;
@@
x = devm_kzalloc(...)
...
?-devm_kfree(d,x);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
the pointers that are allocated with devm_kzalloc will be automatically freed,
at unload time.
Signed-off-by: Devendra Naga <develkernel412222@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tidy up a small typo in the HSI function group list.
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
the allocated memory will be destroyed at the driver unload time,
automatically if driver uses the devm_ functions, so no need of
doing devm_kfree at the error path
Signed-off-by: Devendra Naga <develkernel412222@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It's not so usual, but there are still some cases which require pinctrl
driver function at arch_initcall time. So register imx23 and imx28
pinctrl driver at postcore_initcall time.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Various cleanups to the U300 driver
- Refactor the pin control core to automatically remove
any GPIO ranges when the drivers are removed, instead of
having the drivers do this explicitly.
- Add a function for registering a batch of GPIO ranges.
- Fix a number of incorrect but non-regressive error checks.
- Incremental improvements to the COH901, i.MX and Nomadik drivers
- Add a one-register-per-pin entirely Device Tree-based pin
control driver from Tony Lindgren.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQDUCxAAoJEEEQszewGV1z4EIQAMUREEJG+usUzX/2y9yMvtjn
i3HQLV1UuPYiVyQfkrpwG7yEGYboZg4PoX4MjyTwiJt1Nq6QhHGjncYj8ngL7uSd
B7EvulqH2lhLXdvW6s/nqBf5GfAqAhusLOi3FmyMbt4rnJ5bhFnbIdQ4h5MC7eFf
jwQaDPJWcMPOisNJKAC+McVYpTO+VjivbfqMmQ/B9gmmtGSVoQf6YA3CvjJ0P8IT
Or3xUr1VS6AnkS139qg473pYMKiSDzk9tQaN1k9V37jQvTeDv9ALOrLcJV+Bi002
tfTtmOnPDQskgjz/NQvXuPMykZNT9E+XkjxAT1ClY6YVzrLogcYJxkFH5JQ80Lb5
YMhgciRH92KSzQRsGJrJsH8HkAp3FubbC3rEt1MmkVV9ZPBgcUETGIR5tqcdyh8s
5Hj4VASksTeExi7ajYEcDXDihYOB4l9ApDs+5XNhfPRGDY8sUjoxFLvpdzFXIfhn
UZ5KJt16DoDkq0KVVIx1FHRdCcga+TtpARdi0kl2pzxDRrEti9x3F4nHFgaT4Eqb
osnH17RlO+VGZYtg6635wcxEWr/wMzfzpVOi/0JO2wAm+R5A3VaIqsfvvm+ouRR0
0Q++6NAVHySKTuab8Rz6D0dvTRF8O8zgJowdMDMX52C5nc5fhlKOl/Pc3g0W1q5C
zmCaKOzT9RyPx2l+SrWz
=79Wu
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"These are the accumulated pin control patches for v3.6:
- Various cleanups to the U300 driver
- Refactor the pin control core to automatically remove any GPIO
ranges when the drivers are removed, instead of having the drivers
do this explicitly.
- Add a function for registering a batch of GPIO ranges.
- Fix a number of incorrect but non-regressive error checks.
- Incremental improvements to the COH901, i.MX and Nomadik drivers
- Add a one-register-per-pin entirely Device Tree-based pin control
driver from Tony Lindgren."
* tag 'pinctrl-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: Add one-register-per-pin type device tree based pinctrl driver
pinctrl/nomadik: add spi2_oc1_2 pin group
pinctrl/nomadik: kerneldoc fix
pinctrl/nomadik: use devm_* allocators for gpio probe
pinctrl/nomadik: add pin group to mco function
pinctrl/nomadik: add hsit_a_2 pin group
pinctrl/nomadik: add pin group smcs1 and smps0
pinctrl/nomadik: fix hsir_a_1_pins pin list
pinctrl: pinctrl-imx: fix map setting problem if NO_PAD_CTL is set
pinctrl/coh901: use clk_prepare_[en|dis]able()
pinctrl/pinctrl-tegra: remove IS_ERR checking of pmx->pctl
pinctrl/pinctrl-spear: remove IS_ERR checking of pmx->pctl
pinctrl/u300: drop unused variable
pinctrl: select the proper symbol
pinctrl: add pinctrl_add_gpio_ranges function
pinctrl: remove pinctrl_remove_gpio_range
pinctrl/pinctrl-core: cleanup pinctrl_register
pinctrl/u300: delete pointless debug print
pinctrl/pinctrl-u300: remove devm_kfree at driver unload
We are converting platforms to use the pinctrl framework over time,
rather than using platform specific code for the same effect. This
adds the respective driver for the prima2 platform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIVAwUAUA2dgmCrR//JCVInAQJTqA/7BYaJpsNCKxc2GOVFVtva6Nvq+QaTk9Af
ft2dgEExL5zjaH+HYwLLhdwOFf4Ilwqadw23jtNb2Mqq/FmmO5omenGEWVhTGr7x
RjqWtfgq9PMVh7mZKtTZoC9/vECiX0ZyU3+2Zw+Fn0Begchc1meJGPUbniHwprL6
hLSBC7h+92C5I6WiileE5QNHmkhClQ8Hv9GoLnwR59HSkkspmZNIqsV+vkpPHNaX
GJy3HhT6Xg7KiOLjvvbCjsmt/qgyIKIuJWBzXl1VlnNn0dNDt1Km14DZOdhhXEFv
70IbcZs7ykcJNCApNDH1Hgro69O95phQTJOo6w8FspeAt8UogNTb2uj+lS2GOQHM
rlRfm3XQlXd40Pr8RNCJdg2WWQKGiOhrN+zTuaPovjfTdkdnZkSyhMdrZVT9T7HC
unvsBQ7HXVEwQ0i24d4CqBUscYNRo3iAWjqEAqnXDpDSVrVaJmp9T1LRcX2vF5Lu
nvyLOYYITBkHjkpAjgAoaKdhOBoAq86be0Uo8NjFxVI2881wTSEwdfVOsufTB1HA
L4XGVrc70Bhrk+9Nu4wjXtEz+6tV+6KO+bZdYeCkvwzbCeUo+a0qPqxz7ynBdNbt
FPOToiA8qj6qzkTMl+EeC2bIoYjpbhkMP4V1BsgAjXScuVt2NQdTl8nDJUGtHga6
W590SViMI9U=
=YodD
-----END PGP SIGNATURE-----
Merge tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc pincontrol drivers update from Arnd Bergmann:
"We are converting platforms to use the pinctrl framework over time,
rather than using platform specific code for the same effect. This
adds the respective driver for the prima2 platform."
* tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: prima2: enable gpiolib unconditionally
PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII
This branch contains two kinds of updates: Some platforms in the process
of getting converted to device tree based booting, and the platform
specific patches necessary for that are included here. Other platforms
are already converted, so we just need to update the actual device
tree source files and the binding documents to add support for new board
and new drivers.
In the future we will probably separate those into two branches, and
in the long run, the plan is to move the device tree source files out
of the kernel repository, but that has to wait until we have completed
a much larger portion of the binding documents.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIVAwUAUA2dbmCrR//JCVInAQJl0hAA3U3AnfBBXbKEJhUi47z6QU2kRPVfyjAj
ct+FsZMWFihEHC5/YkB/bQ/i7Hf/AKBZRG6eAUfsyevuhQ0Li+wsRM4eU3FaF6kw
HNqqB6GQWM+2rR8//Y6AAZymTLfe5nbuWFhRXiIggIlQne5jJ1kSidmSzG+OJEuN
sAKXX7Ud5goVsby9Uwp4Gc0fpDsjFmIarhHfMDizFozNZIFzZIhKKdl1VOf+Kv+o
PFRfCGB2KQrrDy0oB62y3iNUiK84LA0xWX4KkI9rD4OHWeiDQpbUITchf//Wa20X
vgZdI8T16sxbmAHi1zerIl8y/CLgLyerp1L3KSMGTwirC+92vZg+jOGYGgNqu973
NOl0IBQFpbAlNzmf52naNgcQ2OxxFQ3ogrlpvE2bItLL7J3vpmn1JwWMTtSrcs3Z
xgbovAq2ivNOiKpzXexvMsWDCU3PxzXaP+2hEUhglJcdXkx5Iwiwi6un2FuF2qWT
l5rSAWkg2kT/OkgYHLBI5JW7e7ugWhUAuCsrIH9eW7xstm4hIlN950vefs2FrZkP
FeE7pn6s6mr98+j9isJKusETXIoEXDLX61vxA8PQP7GYN+/O/g2qB0qztBwarMBL
wAdHCjavOYNwPkxYaGLjv9qKt3X575O/6aFa/NoKGhIECanjLl02Tqg02BdHecST
8HENXCvwQns=
=K3WL
-----END PGP SIGNATURE-----
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann:
"This branch contains two kinds of updates: Some platforms in the
process of getting converted to device tree based booting, and the
platform specific patches necessary for that are included here.
Other platforms are already converted, so we just need to update the
actual device tree source files and the binding documents to add
support for new board and new drivers.
In the future we will probably separate those into two branches, and
in the long run, the plan is to move the device tree source files out
of the kernel repository, but that has to wait until we have completed
a much larger portion of the binding documents."
Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly
added clkdev registers next to a few removed unnecessary ones.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
ARM: LPC32xx: Add PWM to base dts file
ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5
ARM: EXYNOS: Add spi clock support for EXYNOS5
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4
ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock
ARM: ux500: Remove PMU platform registration when booting with DT
ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure
ARM: ux500: Ensure vendor specific properties have the vendor's identifier
pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes
ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled
ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices
ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree
ARM: ux500: Apply ab8500-debug node do the db8500 DT structure
ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices
ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm
ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl
ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT
...
