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Now that slope and offset data are being passed from
device tree no need to populate in driver data.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Add OMAP36xx support to ti-soc-thermal driver. This
chip is also unreliable. The data provided here is
based on OMAP36xx TRM:
http://www.ti.com/lit/ug/swpu177aa/swpu177aa.pdf
Signed-off-by: Eduardo Valentin <edubezva@gmail.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This adds support for OMAP3 chips to ti-soc-thermal. As requested by
TI people, it is marked unreliable and warning is printed.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
DESCRIPTION
Spurious Thermal Alert: Talert can happen randomly while the device remains
under the temperature limit defined for this event to trig. This spurious
event is caused by a incorrect re-synchronization between clock domains.
The comparison between configured threshold and current temperature value
can happen while the value is transitioning (metastable), thus causing
inappropriate event generation. No spurious event occurs as long as the
threshold value stays unchanged. Spurious event can be generated while a
thermal alert threshold is modified in
CONTROL_BANDGAP_THRESHOLD_MPU/GPU/CORE/DSPEVE/IVA_n.
WORKAROUND
Spurious event generation can be avoided by performing following sequence
when the threshold is modified:
1. Mask the hot/cold events at the thermal IP level.
2. Modify Threshold.
3. Unmask the hot/cold events at the thermal IP level.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Bandgap Temperature read Dtemp can be corrupted
DESCRIPTION
Read accesses to registers listed below can be corrupted due to
incorrect resynchronization between clock domains.
Read access to registers below can be corrupted :
• CTRL_CORE_DTEMP_MPU/GPU/CORE/DSPEVE/IVA_n (n = 0 to 4)
• CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA_n
WORKAROUND
Multiple reads to CTRL_CORE_TEMP_SENSOR_MPU/GPU/CORE/DSPEVE/IVA[9:0]:
BGAP_DTEMPMPU/GPU/CORE/DSPEVE/IVA is needed to discard false value and
read right value:
1. Perform two successive reads to BGAP_DTEMP bit field.
(a) If read1 returns Val1 and read2 returns Val1, then
right value is Val1.
(b) If read1 returns Val1, read 2 returns Val2, a third
read is needed.
2. Perform third read
(a) If read3 returns Val2 then right value is Val2.
(b) If read3 returns Val3, then right value is Val3.
The above in gist means if val1 and val2 are the same then we can go
ahead with that value else we need a third read which will be right
since synchronization will be complete by then.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
