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1. pll_base address should return right value
2. uart parent clk is from pll3
Signed-off-by: Yong Shen <yong.shen@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add basic clock support, cpu identification, I/O mapping, interrupt
controller, serial port and ethernet.
Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>