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The network coprocessor (NetCP) is a hardware accelerator available in
Keystone SoCs that processes Ethernet packets. NetCP consists of following
hardware components
1 Gigabit Ethernet (GbE) subsystem with a Ethernet switch sub-module to
send and receive packets.
2 Packet Accelerator (PA) module to perform packet classification
operations such as header matching, and packet modification operations
such as checksum generation.
3 Security Accelerator(SA) capable of performing IPSec operations on
ingress/egress packets.
4 An optional 10 Gigabit Ethernet Subsystem (XGbE) which includes a
3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
per Ethernet port.
5 Packet DMA and Queue Management Subsystem (QMSS) to enqueue and dequeue
packets and DMA the packets between memory and NetCP hardware components
described above.
NetCP core driver make use of the Keystone Navigator driver API to allocate
DMA channel for the Ethenet device and to handle packet queue/de-queue,
Please refer API's in include/linux/soc/ti/knav_dma.h and
drivers/soc/ti/knav_qmss.h for details.
NetCP driver consists of NetCP core driver and at a minimum Gigabit
Ethernet (GBE) module (1) driver to implement the Network device function.
Other modules (2,3) can be optionally added to achieve supported hardware
acceleration function. The initial version of the driver include NetCP
core driver and GBE driver modules.
Please refer Documentation/devicetree/bindings/net/keystone-netcp.txt
for design of the driver.
Cc: David Miller <davem@davemloft.net>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Wingman Kwok <w-kwok2@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The cpsw currently lacks code to properly set up the hardware interface
mode on AM33xx. Other platforms might be equally affected.
Usually, the bootloader will configure the control module register, so
probably that's why such support wasn't needed in the past. In suspend
mode though, this register is modified, and so it needs reprogramming
after resume.
This patch adds a new driver in which hardware interface can configure
correct register bits when the slave is opened.
The AM33xx also has a bit for each slave to configure the RMII reference
clock direction. Setting it is now supported by a per-slave DT property.
This code path introducted by this patch is currently exclusive for
am33xx and same can be extened to various platforms via the DT compatibility
property.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds a driver for the CPTS that offers time
stamping and a PTP hardware clock. Because some of the
CPTS hardware variants (like the am335x) do not support
frequency adjustment, we have implemented this in software
by changing the multiplication factor of the timecounter.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds support for TI's CPSW driver.
The three port switch gigabit ethernet subsystem provides ethernet packet
communication and can be configured as an ethernet switch. Supports
10/100/1000 Mbps.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Sriramakrishnan A G <srk@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
