4 Commits

Author	SHA1	Message	Date
Jianguo Sun	80f8ce5895	clk: hi3798cv200: add COMBPHY0 clock support ... The clock COMBPHY1 has already been supported by hi3798cv200 driver, but COMBPHY0 is missing. It adds COMBPHY0 clock support. Since the mux table is being shared by COMBPHY0 and COMBPHY1, it renames comphy1_mux_p and comphy1_mux_table a bit to drop instance number '1' from there. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>	2018-02-27 09:19:12 +08:00
Shawn Guo	a44d1f531a	clk: hi3798cv200: fix define indentation ... It's a coding-style fix, which corrects the indentation for all those clock definitions, so that the code looks nicer and new definitions can be added with a recommended indentation. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>	2018-02-27 09:19:12 +08:00
Jiancheng Xue	0d84659619	clk: hisilicon: add usb2 clocks for hi3798cv200 SoC ... Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2017-06-21 10:46:45 -07:00
Jiancheng Xue	707d33cb0b	clk: hisilicon: add CRG driver for Hi3798CV200 SoC ... Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2016-11-11 15:43:49 -08:00