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This patch adds sh7343 MSTP enums for mstp_clks[] index.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
In the NUMA or memory hot-add case where system memory has been
partitioned up, we immediately run in to a situation where the existing
PMB entry doesn't cover the new range (primarily as a result of the entry
size being shrunk to match the node size early in the initialization). In
order to fix this up it's necessary to preload a PMB mapping for the new
range prior to activation in order to circumvent reset by MMU.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The minimum section size for the PMB is 16M, so just always error
out early if the specified size is too small. This permits us to
unconditionally call in to pmb_bolt_mapping() with variable sizes
without wasting a TLB and cache flush for the range.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This reworks much of the bootmem setup and initialization code allowing
us to get rid of duplicate work between the NUMA and non-NUMA cases. The
end result is that we end up with a much more flexible interface for
supporting more complex topologies (fake NUMA, highmem, etc, etc.) which
is entirely LMB backed. This is an incremental step for more NUMA work as
well as gradually enabling migration off of bootmem entirely.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Rewinding each debugfs entries to unregister if an error happens.
Based on the commit ca4caa4e1d45f9542fa54263974d0ef637157b4a
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Get rid of div6 clock names on
sh7343/sh7366/sh7722/sh7723/sh7724
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Use clkdev for div6 lookup on SH-Mobile processors:
sh7343/sh7366/sh7722/sh7723/sh7724
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Remove the clock name from sh7722/sh7723/sh7724
hwblk clocks. Lookup is handled by clkdev.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Modify the SuperH clock code to support struct clk
with NULL as name. Such clocks will not be hooked
up to debugfs.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Use clkdev for lookup of hwblk clocks on
sh7722/sh7723/sh7724.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Modify sh7722/sh7723/sh7724 to use clkdev for
TMU and SCIF clock lookups.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Rework the sh7722/sh7723/sh7724 hwblk code to use the
hwblk id as index in the mstp clock array.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This reworks the memory limit handling to tie in through the available
LMB infrastructure. This requires a bit of reordering as we need to have
all of the LMB reservations taken care of prior to establishing the
limits.
While we're at it, the crash kernel reservation semantics are reworked
so that we allocate from the bottom up and reduce the risk of having
to disable the memory limit due to a clash with the crash kernel
reservation.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This plugs in a memory init callback in the machvec to permit boards to
wire up various bits of memory directly in to LMB. A generic machvec
implementation is provided that simply wraps around the normal
Kconfig-derived memory start/size.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The elfcorehdr parsing was just tossed in setup.c, but nothing outside of
the crash dump code/vmcore bits require it, so we just move it out of the
way, as per ppc.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
There's still quite a bit of shootdown logic that needs to be hacked up
to support SMP for kdump properly, so just add in a BROKEN_ON_SMP
dependency for now.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This bumps up the extra LMB reservations in ordering so that they're
accounted for prior to iterating over the region list. This ensures that
reservations are visible both within the LMB and bootmem context.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Various boot loaders go to various extents to thwart the initrd detection
logic (mostly on account of not being able to be bothered with adhering
to the established boot ABI), so we make the detection logic a bit more
robust. This makes it possible to work around the SDK7786's firmware's
attempts to thwart compressed image booting. Victory is mine.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The breakpoint generic layer assumes that archs always know in advance
the static number of address registers available to host breakpoints
through the HBP_NUM macro.
However this is not true for every archs. For example Arm needs to get
this information dynamically to handle the compatiblity between
different versions.
To solve this, this patch proposes to drop the static HBP_NUM macro
and let the arch provide the number of available slots through a
new hw_breakpoint_slots() function. For archs that have
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS selected, it will be called once
as the number of registers fits for instruction and data breakpoints
together.
For the others it will be called first to get the number of
instruction breakpoint registers and another time to get the
data breakpoint registers, the targeted type is given as a
parameter of hw_breakpoint_slots().
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Cc: K. Prasad <prasad@linux.vnet.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Jason Wessel <jason.wessel@windriver.com>
Cc: Ingo Molnar <mingo@elte.hu>
There are two outstanding fashions for archs to implement hardware
breakpoints.
The first is to separate breakpoint address pattern definition
space between data and instruction breakpoints. We then have
typically distinct instruction address breakpoint registers
and data address breakpoint registers, delivered with
separate control registers for data and instruction breakpoints
as well. This is the case of PowerPc and ARM for example.
The second consists in having merged breakpoint address space
definition between data and instruction breakpoint. Address
registers can host either instruction or data address and
the access mode for the breakpoint is defined in a control
register. This is the case of x86 and Super H.
This patch adds a new CONFIG_HAVE_MIXED_BREAKPOINTS_REGS config
that archs can select if they belong to the second case. Those
will have their slot allocation merged for instructions and
data breakpoints.
The others will have a separate slot tracking between data and
instruction breakpoints.
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Cc: K. Prasad <prasad@linux.vnet.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@elte.hu>
The current policies of breakpoints in x86 and SH are the following:
- task bound breakpoints can only break on userspace addresses
- cpu wide breakpoints can only break on kernel addresses
The former rule prevents ptrace breakpoints to be set to trigger on
kernel addresses, which is good. But as a side effect, we can't
breakpoint on kernel addresses for task bound breakpoints.
The latter rule simply makes no sense, there is no reason why we
can't set breakpoints on userspace while performing cpu bound
profiles.
We want the following new policies:
- task bound breakpoint can set userspace address breakpoints, with
no particular privilege required.
- task bound breakpoints can set kernelspace address breakpoints but
must be privileged to do that.
- cpu bound breakpoints can do what they want as they are privileged
already.
To implement these new policies, this patch checks if we are dealing
with a kernel address breakpoint, if so and if the exclude_kernel
parameter is set, we tell the user that the breakpoint is invalid,
which makes a good generic ptrace protection.
If we don't have exclude_kernel, ensure the user has the right
privileges as kernel breakpoints are quite sensitive (risk of
trap recursion attacks and global performance impacts).
[ Paul Mundt: keep addr space check for sh signal delivery and fix
double function declaration]
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Cc: K. Prasad <prasad@linux.vnet.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Jason Wessel <jason.wessel@windriver.com>
Cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Tag ptrace breakpoints with the exclude_kernel attribute set. This
will make it easier to set generic policies on breakpoints, when it
comes to ensure nobody unpriviliged try to breakpoint on the kernel.
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Cc: K. Prasad <prasad@linux.vnet.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@elte.hu>
arch/sh/kernel/smp.c:164: error: conflicting types for 'native_cpu_disable'
/home/matt/src/kernels/sh-2.6/arch/sh/include/asm/smp.h:48: error: previous declaration of 'native_cpu_disable' was here
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add CONFIG_VIRTUALIZATION to the SH architecture
and include the virtio code there. Used to enable
the virtio drivers under QEMU.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The UP dependency was inherited from ARM, which seems to have run in to
it due to the stacktrace code not being available for SMP in certain
cases, as we don't have this particular limitation there is no specific
need to block on the SMP dependency.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This wires up CPU hotplug for SH-X3 SMP CPUs. Presently only secondary
cores can be hotplugged given that the boot CPU has to contend with the
broadcast timer. When real local timers are implemented this restriction
can be lifted.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This provides a cache of the secondary CPUs idle loop for the cases where
hotplug simply enters a low power state instead of resetting or powering
off the core.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
smp_store_cpu_info() is presently flagged as __init, but is called by
start_secondary() which is __cpuinit, fix it up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This iterates over the maximum number of CPUs we plan to support and
makes sure they're all set in the present CPU map.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This converts from cpu_set() for the online map to set_cpu_online().
The two online map modifiers were the last remaining manual map
manipulation bits, with this in place everything now goes through
cpumask.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the platform ops migration, the definitions still need to be
included in the CONFIG_SMP=n case, so make the asm/smp.h include
explicit.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
When registering CPUs in the topology initialization ensure that all of
the present CPUs are flagged as hotpluggable.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that compressed image loading is possible for sdk7786, drop the
vmlinux.bin default image target and update the defconfig accordingly.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch updates the sh7751 pci code to handle io ports
correctly. The code is based on the sh7788x implementation.
Tested on a R2D-1 board with CONFIG_8139TOO_PIO=y.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Update the R2D defconfigs to bump up the maximum
number of SCIF ports on the system.
Fixes a broken serial console regression added
by cd5f107628ab89c5dec5ad923f1c27f4cba41972.
Reported-by: Shin-ichiro KAWASAKI <kawasaki@juno.dti.ne.jp>
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Alexandre Courbot <alex@dcl.info.waseda.ac.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CHCR_TS_HIGH_SHIFT is defined as a shift of TS high bits in CHCR register,
relative to low bits. The TS_INDEX2VAL() macro has to take this into account.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/mfleming/sh-2.6:
sh: Use correct mask when comparing PMB DATA array values
sh: Do not try merging two 128MB PMB mappings
sh: Fix zImage load address when CONFIG_32BIT=y
sh: Fix address to decompress at when CONFIG_32BIT=y
sh: Assembly friendly __pa and __va definitions
Lists of DMA channels and slaves are not changed, make them constant. Besides,
SH7724 channel and slave configuration of both DMA controllers is identical,
remove the extra copy of the configuration data.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
As explained in commit 1c0fe6e3bd, we want to call the architecture independent
oom killer when getting an unexplained OOM from handle_mm_fault, rather than
simply killing current.
Cc: linux-sh@vger.kernel.org
Cc: linux-arch@vger.kernel.org
Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: David Rientjes <rientjes@google.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Previously we were masking the PMB DATA array values with the value of
__MEMORY_START | PMB_V, which misses some PFN bits off the mask.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
