2 Commits

Author	SHA1	Message	Date
Jayesh Choudhary	c024c46fe1	arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_main ... Add the address space for SA3UL to the ranges property of the cbass_main node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220412075008.10553-1-j-choudhary@ti.com	2022-04-29 12:36:46 +05:30
Vignesh Raghavendra	f1d17330a5	arm64: dts: ti: Introduce base support for AM62x SoC ... This add bare minimum DT for AM62 describing ARM compute clusters, Main, MCU and Wakeup domain and interconnects, UARTs and I2Cs to enable booting using ramdisk. Hierarchy of dts files: am62.dtsi: base SoC skeleton which is common across am62xx family of SoCs, includes am62-main.dtsi, am62-mcu.dtsi and am62-wakeup.dtsi representing 3 domains and peripherals in each of these domain am625.dtsi: describes CPU cluster (Quad A53s). Since, am625 is a current superset device with all peripherals, am625.dtsi includes am62.dtsi completing SoC definition. Individual EVMs using this SoC will just need to include am625.dtsi thus making things easier for Board and SOM Vendors. Future derivative SoCs will have their own am62{1-9}{1-9}.dtsi overriding cluster / peripheral definitions with their own compatibles. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Co-developed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220225120239.1303821-5-vigneshr@ti.com	2022-02-28 05:34:43 -06:00