IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
Document DT bindings for Analog Devices as3645a flash LED controller which
also supports an indicator LED.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Dongwoon DW9714 is a voice coil lens driver.
Also add a vendor prefix for Dongwoon for one did not exist previously.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Since i80/command mode is determined in runtime by propagating info
from panel this property can be removed.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This adds the necessary data for handling io voltage domains on the RV1108.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Add support to the keystone remoteproc driver for managing the
DSP present in the Keystone 2 66AK2G SoC. The 66AK2G SoC has
a Power Management Micro Controller (PMMC) that manages the
individual device's power, clock and reset functionalities.
The keystone remoteproc driver already uses standard frameworks
for reset and clock control, so it doesn't require any significant
modifications other than a new compatible suitable for 66AK2G DSP.
The binding document is also updated to reflect the modified
property values used by the 66AK2G DSP node as compared to the
values used by existing Keystone 2 DSPs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the device tree bindings document for the DSP processor
subsystem devices on TI Davinci DA8xx/OMAP-L13x SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Sapphire som+baseboard which is another evaluation board for Rocckhip
customers and the rk3399-based som+baseboard from Austria-based
Theobroma Systems, which interestingly is in a miniITX formfactor
and provides a real PCIe x4 slot.
New nodes include on rk3399 graphics (vops, hdmi, etc) and more iommus,
on rk3328 iommus, pwm, thermal management, and sound as well as operating
points and rk3368 got iommu nodes and cpu operating points.
On existing boards firefly got operating points, the rk3328-evb got its
pmic and gru boards got some sound-related fixes.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmdnagQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgSpBB/9v6flM/QtBVeXhR1tfrXIt3veUaiwiTwhg
PIj6J7EJZCgA9TiHr4zcQzjCx581a9v1rUEpnhZyi7d/zrNurpJRYtBNcqfDS28Z
kyL30gwf/y4nVAzgIODGMNRWe3+IETNCIRZ236cV7jr9HgKmHvA0qc2aMzjHPMCF
XS9wPXgEW1kYIgKqzq1drAWY3iVB0W37KMX9HKVQfAlPcGu5jobk0lruQBZV0InH
8NR3NB9a7eknzPejmBO2ga0idS0oAc/eFQ8h2bHrxWVm1JO+2QDc7epxWCTmxBcP
DLy+7tuQiXEFc25AM3QpW97pJuqDT+zeZXd/F5BK5uGnpH63SNbi
=D65g
-----END PGP SIGNATURE-----
Merge tag 'v4.14-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "second round of Rockchip dts64 changes for 4.14" from Heiko Stübner:
3 new boards, the rk3328-based Rock64 from the Pine64-makers, the
Sapphire som+baseboard which is another evaluation board for Rocckhip
customers and the rk3399-based som+baseboard from Austria-based
Theobroma Systems, which interestingly is in a miniITX formfactor
and provides a real PCIe x4 slot.
New nodes include on rk3399 graphics (vops, hdmi, etc) and more iommus,
on rk3328 iommus, pwm, thermal management, and sound as well as operating
points and rk3368 got iommu nodes and cpu operating points.
On existing boards firefly got operating points, the rk3328-evb got its
pmic and gru boards got some sound-related fixes.
* tag 'v4.14-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (29 commits)
arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
dt-bindings: add rk3399-q7 SoM
arm64: dts: rockchip: add rk3328-rock64 board
arm64: dts: rockchip: add rk3328 pdm node
arm64: dts: rockchip: add more rk3399 iommu nodes
arm64: dts: rockchip: add rk3368 iommu nodes
arm64: dts: rockchip: add rk3328 iommu nodes
arm64: dts: rockchip: Add basic cpu frequencies for RK3368
arm64: dts: rockchip: add rk805 node for rk3328-evb
arm64: dts: rockchip: Assign mic irq to correct device for Gru
arm64: dts: rockchip: init rk3399 vop clock rates
arm64: dts: rockchip: Add pwm nodes for rk3328
arm64: dts: rockchip: Fix wrong rt5514 dmic delay property for Gru
arm64: dts: rockchip: disable tx ipgap linecheck for rk3399 dwc3
arm64: dts: rockchip: remove num-slots property from rk3399-sapphire
arm64: dts: rockchip: Enable tsadc module on RK3328 eavluation board
arm64: dts: rockchip: add thermal nodes for rk3328 SoC
arm64: dts: rockchip: add tsadc node for rk3328 SoC
arm64: dts: rockchip: add rk3328 i2s nodes
...
(usb, operating points, spi, pwm, adc, watchdog, i2c and devices for
its evb).
RK3228/3229 gets iommu and spi nodes. Similar to the rk3288 which
also gets some more iommu nodes as well as getting converted to 64
bit addresses due to wanting to address more than 4GB of memory
via LPAE.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmdoA4QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgeBtB/9oM4MmVRJ0YX7hk4NuU9c4HHdvCW0f1rJe
Q6rE6dP7fW3J27d6PuySVWzvIBmD+3xVA2t0dDm85DIP8f1DFz3vyNhkEsu1VG89
MULTektihczugCy+sh3iHILs4fLXJ8QUjCKJWOcWmZHOaXNXXjJIVjC97m5F4ZAj
KVOYXNnCKdaHYIeP0lkjStL8Z9Ua7svkjfgsSPTGTSJQQ+bGcd/8JnmlkzjfHWLw
qNz6M7FPoJ1rAffskr1At27oRs7UAVSKNAejl8DWKvLXml6NQPRRRu99sLLanxII
3b6LsC6Vwea4a1Rjwx0LZWdDUtB1W34/ZIEw4JceK/i6HfV5K2Oi
=di6U
-----END PGP SIGNATURE-----
Merge tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "second round of Rockchip dts32 changes for 4.14" from Heiko Stübner:
A lot of attention for the rv1108 soc targetted at media-processing
(usb, operating points, spi, pwm, adc, watchdog, i2c and devices for
its evb).
RK3228/3229 gets iommu and spi nodes. Similar to the rk3288 which
also gets some more iommu nodes as well as getting converted to 64
bit addresses due to wanting to address more than 4GB of memory
via LPAE.
* tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: rockchip: add cpu power supply for rv1108 evb
ARM: dts: rockchip: add cpu opp table for rv1108
ARM: dts: rockchip: add rk322x iommu nodes
ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
ARM: dts: rockchip: add pwm backlight for rv1108 evb
ARM: dts: rockchip: add pwm dt nodes for rv1108
ARM: dts: rockchip: add spi dt node for rv1108
ARM: dts: rockchip: add saradc support for rv1108
ARM: dts: rockchip: add watchdog dt node for rv1108
ARM: dts: rockchip: add i2c dt nodes for rv1108
clk: rockchip: fix up indentation of some RV1108 clock-ids
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
clk: rockchip: add more clk ids for rv1108
ARM: dts: rockchip: add more iommu nodes on rk3288
ARM: dts: rockchip: convert rk3288 device tree files to 64 bits
ARM: dts: rockchip: add spi node and spi pinctrl on rk3228/rk3229
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Allwinner A10 is now driven by sunxi-ng CCU driver.
Add devicetree binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner A20 is now driven by sunxi-ng CCU driver.
Add devicetree binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds the base Device Tree files for the Armada 8KPlus.
The Armada 8KP SoCs include several hardware blocks, and this
commit only adds support for the AP810 block, that contains the CPU
core and basic peripherals.
AP810 is a high-performance die, includes octal core application
processor based ARMv8-A architecture, two standard high speed DDR4
interface, and GIC-600 interrupt controller.
AP810 Built as part of Marvell’s MoChi AP family products.
Armada-8080 (8KPlus family), include an AP810 block that contains
the CPU core and basic peripherals.
This commit creates the following hierarchy:
* armada-ap810-ap0.dtsi - definitions common to AP810
* armada-ap810-ap0-octa-core.dtsi - description of the octa cores
* armada-8080.dtsi - description of the 8080 SoC
* armada-8080-db.dts - description of the 8080 board
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
- Add more module clocks for R-Car V2H and M3-W,
- Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
- Add support for the new R-Car D3 SoC,
- Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
- Small fixes and cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZlVHhAAoJEEgEtLw/Ve77wqwP/1/RgfVlAoAHDL+aIo5FacVk
uL5XPembCm7lCB+9OIU7GIrZQbZGWFBRUfL4oqOSfxqsTLv9gAKyZNUBETOKijXo
NW0m6gkpN2+AZvZlTsZUzYLgdakNdOXi5atYn41zvAy2wbtww2aUqUHvwHz2PKjz
k4ucRJEjljVGzTMu5/yqaADioEnTnb9FZ+uRGiy0/W+sD4UoEum75Ay6u3t7s0bL
cmA2rtCFg52GlvC+BsZHntAjTHlSFXn7W8LddP1sb0oVvc9spC3k8q4DR8zVGNU2
VCk6XKyOnWTpHjyw/IYBAjQ+nNainklLyIusnEnG0VyUZY0pvFcC/SOAHxO4NSBS
AJqD7ylhkc6gnYL0lqp+n6RJaoY4GOhpSFz+NNtPXFXaDUfuf+WTiYzHnrrCCZ4z
jTGcmiynl229jAxN5fYudjfnbydBfvdKGINtVRI7ApP+oZa5K0Wzbd4ZDx4Q2mML
90mCdy+BVFGUcosh91kpL9vKazEm8EBYArMVhRDTFog6c4VyUrzL77fWleoptc4M
yWlWB/KwfAhr0/NM1cxguax9bG1eOJbwq5FxHGwUqUCjxUxUWItNM9E1RMJ89drm
zIsRO3CseOVFJcsm/75owYc/vXNbWcZ09wHyt8RExygPUPxRj3iCCvI5Y+tDqDIG
zb2H5/e0HI7PjHt+hLEW
=77l6
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
* Add more module clocks for R-Car V2H and M3-W,
* Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
* Add support for the new R-Car D3 SoC,
* Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
* Small fixes and cleanups.
* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add USB3.0 clock
clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
clk: renesas: cpg-mssr: Add R8A77995 support
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
clk: renesas: Add r8a77995 CPG Core Clock Definitions
clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
clk: renesas: rcar-gen3-cpg: Drop superfluous variable
clk: renesas: Allow compile-testing of all (sub)drivers
clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
clk: renesas: div6: Document fields used for parent selection
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).
Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmcl8sQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgeiBB/wIf5LHDu09HuOb1bjtYASMc//ve2ymhpd7
QsccJ0nteJTWnYQlrJUPYN8YhRVqPNrz7Fq8PkMMkzm89fQQ6lr5DxOy6olKTPM4
sGf+242eE3XttHjJxcshNPS98A56zBa9OgNC9sUsTex8r7NaJn+Gvlf0sXEgQRQi
5FprJf49/4rlHZypVMg1j+aMEWM8ZAmXLP3F77Qch+rfxE74POV9/HI7EEoSQ9MX
TxwEewmM8IGXY9aVTvtADPmX31CgdOD3qm4giwGkBf2F8SajP8R63wi+BYpNfUTX
+TrexLXEfeKEVtU+xPXsNYmEnAOW6sRvfyUnq4oA1hVSnFoexFA1
=Upwy
-----END PGP SIGNATURE-----
Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk driver updates from Heiko Stuebner:
The biggest change is fixing the jitter on the fractional clock-type
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).
Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).
* tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rv1108 clk_mac sel register description
clk: rockchip: rename rv1108 macphy clock to mac
clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks
clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id
clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID
clk: rockchip: add rk3228 sclk_sdio_src ID
clk: rockchip: add special approximation to fix up fractional clk's jitter
clk: fractional-divider: allow overriding of approximation
clk: rockchip: modify rk3128 clk driver to also support rk3126
dt-bindings: add documentation for rk3126 clock
clk: rockchip: add some critical clocks for rv1108 SoC
clk: rockchip: rename some of clks for rv1108 SoC
clk: rockchip: fix up some clks describe error for rv1108 SoC
clk: rockchip: support more clks for rv1108
clk: rockchip: fix up the pll clks error for rv1108 SoC
clk: rockchip: support more rates for rv1108 cpuclk
clk: rockchip: fix up indentation of some RV1108 clock-ids
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
clk: rockchip: add more clk ids for rv1108
Usual improvements:
- Added support for fixed post-divider on divider and NKM-style clocks
- Added driver for R40 CCU
Non critical fixes (from round 1):
- Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
- Make fractional clock modes really used and correctly configured
- Make H3 cpu clock rate change correctly to be used with cpufreq
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAlmaR6AOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDC8YA//aLULoosISnyHs+wKowVHuDb7/mQ82O1gOAxC
oE/vscd/WCRm7A5tfy+xHfajX/YRf32Qc09wB7fxUF4R0lgkO9QjUO0yX74a6bPh
HCh/+bcmeNl9TZAYpTs72Q4nfc1x63OZwxMqTRnBmh3cevyIBJiFvqPjoMeD+Ari
n32QEBgGE+A8bWshVFpNFyId6iyfMfozSYninIkVkwMGr7QgBgJRK1/5sftyZMR+
NQ2IGkaUfICnXofF//pNKsH7TN770gyDtFVWjrKZMrEKoP+gp3mawzMpfePKH/O6
4ihcm5LOo1Kdg5UzRTpQ2B/9fNUn2EvFYT6RuIBfddQcaflT1AzWtNK52j2L/crD
tFyamcCSsNY5LzeySbVW+pQMRfrq6UCYtssiL7HYEcwMzvv61PfyDtKq5dxtJd0Q
W8S6wPE/foj0i0JQWs0K70AacGU6XdEanUAtc5r3AsniCwwOtlwnaQqOlE5CiwAo
HOSItOxX4Y/9QglnntsDyhNUaKpaSiG21XdE3ho3xq1/CS9ED3p5Ljbshem5fnPi
mPisF6Ca6NVvCZ+sjH2RVvmGyh3d+BPfQLWC/sTamC4rnpDalrMq6IsCOivzbxqQ
ltkYwUO1nmz5NMloeWYCUWWmLUOECCQu7Mppf2UQxpidrEEY0mbBYFdOlehrlHZT
bWt2NdQ=
=DKSp
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock changes from Chen-Yu Tsai:
* Added support for fixed post-divider on divider and NKM-style clocks
* Added driver for R40 CCU
* Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
* Make fractional clock modes really used and correctly configured
* Make H3 cpu clock rate change correctly to be used with cpufreq
* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: support R40 SoC
dt-bindings: add compatible string for Allwinner R40 CCU
clk: sunxi-ng: nkm: add support for fixed post-divider
clk: sunxi-ng: div: Add support for fixed post-divider
dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Wait for lock when using fractional mode
clk: sunxi-ng: Make fractional helper less chatty
clk: sunxi-ng: multiplier: Fix fractional mode
clk: sunxi-ng: Fix fractional mode for N-M clocks
clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0
which uses BAM DMA Engine while IPQ806x uses EBI2 NAND
which uses ADM DMA Engine.
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
BAM DMA.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
1. Correct the compatible string for IPQ806x
2. Change the NAND controller and NAND chip nodes name
for more clarity.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
to provide additional features that are not covered by GIC. The main
purpose is to provide logic inverter to support low level and falling
edge trigger types for interrupt lines from on-board devices.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
RK3399-Q7 is a Qseven compatible system-on-module by Theobroma Systems.
This adds the module and the EVK baseboard "Haikou"
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds the compatible of GRF and USBGRF for RV1108 SoCs.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
TI AMC6821 fan controller and Intersil ISL1208 are trivial
devices, so add them to the binding list.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Theobroma Systems is a design house specialized in embedded systems
and a manufacturer of system-on-modules.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The ROCK64 is a credit card size 4K60P HDR Media Board Computer using the
Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting
up to 4GB 1600MHz LPDDR3 memory. It provides eMMC module socket, MicroSD
Card slot, Pi-2 Bus, Pi-P5+ Bus, USB 3.0 and many others peripheral
devices interface for makers to integrate with sensors and devices.
The devicetree currently supports basic peripherals, with more to be
added later on.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch documents the new marvell,system-controller property used by
the Marvell ppv2 network driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
*) Add USB PHY driver for Ralink SoC
*) Make phy-mt65xx-usb3 driver support PCIe and SATA phy
*) Add mediatek directory and rename phy-mt65xx-usb3 to phy-mtk-tphy.c
since it now supports USB3.0, PCIe and SATA PHYs
*) Make sun4i-usb-phy driver support USB PHYs for A83T SoC
*) Make phy-qcom-qmp driver support USB PHYs for IPQ8074 SoC
*) Make rockchip-inno-usb2 driver support usb2-phy for rv1108 SoC
*) Minor fixes in phy drivers
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJZm7g9AAoJEA5ceFyATYLZYBgP/2j6uqbx1d+XrxJViXdT1WOE
tpmtwTLSH6qTDcxHr11NaG3xqzuJQz84Jja2D4q6FV9dPSuC7JiBTddRdIHHyOcn
nnzOnytL84zinYpaDm4xT45LV7ZqTJVnUtWJkrcqNpeGEXL7NRbR50Xsm8LI9lXT
iRnuNyxPXPSAdxPcmz48j+gXwOYBAVM9u2z11C2ciydya8Fs8tbu1Mf5VIpLKunQ
5RlQDHLDBN1SmSNp1OOc7N7E7kQe0Cu7lBbWVEyeDGber588MaiFSf/QXcOJ9ceK
TmcNkQhDcnnWNuDIBnlkHcp+f5NnKI3E5qLyJ16IXqiEOcGh6q6qU2R7RuAd8mUp
9ixIRhznm6Zsqv139TJvYZsvwDh9vbfyt7UB1GHEpkSI2mpQnwYKTKW2mLa0dD2P
0PBihdIAlfGJCyIJBVaGHzvimikIqnVOsNKHoHLaWMBO4B35VACZjjD0hTQnttPp
PRohLWnG5WleqJR3BdlVVGAGyvkDFFWjjqDbUQwKzzSYLsgZd0IA7CETjKWlKgVn
HhmVge2g58Gz3oxiVoKMrYvL/22n/gT77MiYiwuDv4cYjXvNlVTM0Cctiacz2uFk
nmjfEn3uRhgTslcBiqArbBLPzA8IjSIKxjqelrwvzLp43092pLN1OsIGnFmKZVLr
tRIYc1xyLSdGLbcGngbz
=SckR
-----END PGP SIGNATURE-----
Merge tag 'phy-for-4.14_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
phy: for 4.14
*) Add USB PHY driver for Ralink SoC
*) Make phy-mt65xx-usb3 driver support PCIe and SATA phy
*) Add mediatek directory and rename phy-mt65xx-usb3 to phy-mtk-tphy.c
since it now supports USB3.0, PCIe and SATA PHYs
*) Make sun4i-usb-phy driver support USB PHYs for A83T SoC
*) Make phy-qcom-qmp driver support USB PHYs for IPQ8074 SoC
*) Make rockchip-inno-usb2 driver support usb2-phy for rv1108 SoC
*) Minor fixes in phy drivers
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
It only supports rmii interface. Add constants and callback functions
for the dwmac on rv1108 socs. As can be seen, the base structure is
the same, only registers and the bits in them moved slightly.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Renesas RZ/G1E (R8A7745) SoC GPIO blocks are identical to the R-Car Gen2
family. Add support for its GPIO controllers.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Propagate errors on group config, now r8a7740-armadillo800eva.dts is
fixed,
- Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0,
- Add USB2.0 and USB3.0 pin groups on R-Car M3-W,
- Add a missing MMC pin group on R-Car M2-W and RZ/G1M,
- Add initial support for R-Car D3,
- Small fixes and cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZlWFUAAoJEEgEtLw/Ve77evIP/RIdkXo3MM9fHmbDUbpPFHH/
AY/8hwBh0r2ayfxoIzsj4EuRlOLgebrusa0VEFSp6kMOhuN2EB9wMMjnGG96I5Ld
8LoWEqddG9btxvWIRjaC7j1VBz3clU7RLb6nIWzY9sW0L8xJ7Dk6P+gudRQqu9VU
RRCdj8RCx3tFtWRgfJOXnlHSQo1H/okDa7V2H8NddVDLHNMb5400kUaJnFG9CpMl
YNqrU8yVSs3vYCZxvNxchL0IcxSNuhwkMA2OHw8iNxuTZuDvNpIiHDfCNPmmqnlk
4FFFNEKf6No1Y/726ba3tKSIMUTCS8FXel+nRxea9vTpx5smTfy3BH5ngcD9JJHA
aeuhlGKBtgyMhJ839SOfTbFwosvdSjvf41NtaKDtLD8AwB2MxI0jfCaa4+M3McVv
gSgF0lQczg3PHPv6s1DnJGmOGCbwvgxp61jYNzrKziZXfKtTCZd8PFY9v+/Tgr0H
5+6Z17LR5/eNszxZVAV7V8WMTa6rME7rooyEG4f+ZnU09S7fDohWEkMDTRBY5Kna
9X9pHiDytsfRGhMwewr2HYabu3RoLLLBCJGXg4L9DuMeN0+tLLlxNm+jkaVM8gyG
gC4SdTOucyF5z3K7o7TrAdBktMPJZjY9LhGtazS6dtG1gvFhpZoky5lJJr9CQk05
0EooaisR3ONv/LRAw6AH
=xgLM
-----END PGP SIGNATURE-----
Merge tag 'sh-pfc-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.14
- Propagate errors on group config, now r8a7740-armadillo800eva.dts is
fixed,
- Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0,
- Add USB2.0 and USB3.0 pin groups on R-Car M3-W,
- Add a missing MMC pin group on R-Car M2-W and RZ/G1M,
- Add initial support for R-Car D3,
- Small fixes and cleanups.
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This adds support usb2-phy for rv1108 SoCs and amend phy Documentation.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add otg-mux property to support multiplexed interrupt in otg-port
on some Rockchip SoC (e.g RV1108).
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add rockchip,usbgrf property to support the registers of usb-phy
that are distributed in grf and usbgrf on some special Rockchip
SoCs (e.g RV1108).
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
Add a compatible string for it, and describe the needed properties.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
regions, clocks, resets, and optional vbus properties. These were
not described when the H3 compatible string was added.
Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
found on the H3 SoC")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Provide support for controlling reset pin. If this is not driven
correctly the device will be held in reset and will not respond.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
MBHC (MultiButton Headset Control) support is available in pm8921 in two
blocks, one to detect mechanical headset insertion and removal and other
block to support headset type detection and 5 button detection and othe
features like impedance calculation.
This patch adds support to:
1> Support to NC and NO type of headset Jacks.
2> Mechanical insertion and detection of headset jack.
3> Detect a 3 pole Headphone and a 4 pole Headset.
4> Detect 5 buttons.
Tested it on DB410c with Audio Mezz board with 4 pole and 3 pole
headset/headphones.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch adds bindings in DT to provide required micbias voltage which
could be specific to board. With this new binding, now the mic bias
voltage is left at hardware default value if the device tree does not
specify any mic bias voltage value. Correct micbias value is required
for mbhc buttons to work.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The sun8i-h3 introduces a lot of changes to the i2s block such
as different register locations, extended clock division and
more operational modes. As we have to consider the earlier
implementation then these changes need to be isolated.
None of the new functionality has been implemented yet, the
driver has just been expanded to allow it work on the H3 SoC.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
pdm sdi0~3 pins are optional, for example, if 4ch required,
only sdi0~1 need to be enabled.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Enhance the MediaTek PWM binding with details about the IP found in the
MT2712 and MT7622 SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
