8098 Commits

Author SHA1 Message Date
Brian Norris
ef087b7ecf clk: rockchip: rk3399: make CPU clocks critical
The CPU clocks don't currently have any owner (e.g., cpufreq-dt doesn't
enable() them -- and even if it did, it's not early enough compared to
other consumers -- nor does arch/arm64/kernel/smp.c), and instead are
simply assumed to be "on" all the time.

They are also parents of a few other clocks which haven't been
previously exposed for other devices to consume. If we want to expose
those clocks, then the common clock framework may eventually choose to
disable their parents (including the CPU PLLs) -- which is no fun for
anyone.

Thus, mark the CPU clocks as critical, to prevent them from being
disabled implicitly.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210908111337.v2.1.I006bb36063555079b1a88f01d20e38d7e4705ae0@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-09-20 15:12:23 +02:00
Abel Vesa
f121cca26c clk: imx: Rework all clk_hw_register_gate wrappers
Instead of having multiple inline functions that were calling
clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate
and implement the rest as macros that pass on as arguments whatever
is needed in each case.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/1631521490-17171-4-git-send-email-abel.vesa@nxp.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17 10:43:31 +03:00
Abel Vesa
4e6b7e7538 clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones
Implement the clk based helpers as macros rather than as inline
functions. Once all the provider drivers have switch to clk_hw,
all the clk based macros will go away.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/1631521490-17171-3-git-send-email-abel.vesa@nxp.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17 10:43:27 +03:00
Abel Vesa
536559af6a clk: imx: Remove unused helpers
Remove all the helpers that are not referenced anywhere
anymore. Most of them are not clk_hw based. The rest are
passing the device as an argument and were intented for
BLK_CTL driver usage, but that is not the case anymore since
the BLK_CTL is (or will be) implemented outside of CCF.

 - imx_clk_divider2
 - imx_clk_gate2_shared2
 - imx_clk_gate3
 - imx_clk_gate4
 - imx_clk_frac_pll
 - imx_clk_sscg_pll
 - imx_clk_pll14xx
 - imx_clk_pll14xx
 - imx_clk_divider2_flags
 - imx_dev_clk_hw_gate
 - imx_dev_clk_hw_gate_shared
 - imx_clk_gate3_flags
 - imx_clk_gate4_flags
 - imx_dev_clk_hw_mux
 - imx_clk_mux2
 - imx_dev_clk_hw_mux_flags
 - imx8m_clk_composite_flags
 - __imx8m_clk_composite
 - imx8m_clk_composite
 - imx8m_clk_composite_critical

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/1631521490-17171-2-git-send-email-abel.vesa@nxp.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2021-09-17 10:43:12 +03:00
Stephen Boyd
a8cd038cac clk: mediatek: Export clk_ops structures to modules
modpost complains once these drivers become modules.

 ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined!

Let's just export them.

Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Miles Chen <miles.chen@mediatek.com>
Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build")
Link: https://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:57:23 -07:00
Christophe JAILLET
af9617b419 clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths
If we exit the for_each_of_cpu_node loop early, the reference on the
current node must be decremented, otherwise there is a leak.

Fixes: f756e362d938 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/545df946044fc1fc05a4217cdf0054be7a79e49e.1619161112.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:25:16 -07:00
Miles Chen
f09b9460a5 clk: mediatek: support COMMON_CLK_MT6779 module build
To support COMMON_CLK_MT6779* module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210901222526.31065-4-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:20:21 -07:00
Miles Chen
32b028fb1d clk: mediatek: support COMMON_CLK_MEDIATEK module build
To support COMMON_CLK_MEDIATEK module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210901222526.31065-3-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:20:20 -07:00
Miles Chen
7c971695cb clk: composite: export clk_register_composite
To support module build of mediatek clk drivers,
it is necessary to export clk_register_composite.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210901222526.31065-2-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:19:35 -07:00
Rob Herring
69bfe08f23 clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address
The ICST binding now also supports 'reg' in addition to 'vco-offset' for
the VCO register address. Add support to the driver to get the VCO
address from 'reg'.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210913192816.1225025-6-robh@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 18:11:23 -07:00
Chun-Jie Chen
74e1652ce9 clk: mediatek: Add MT8195 apusys clock support
Add MT8195 apusys clock controller which provides PLLs
in AI processor Unit.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
222e0fbcef clk: mediatek: Add MT8195 imp i2c wrapper clock support
Add MT8195 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-24-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
993e9a77e2 clk: mediatek: Add MT8195 wpesys clock support
Add MT8195 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-23-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
50df772268 clk: mediatek: Add MT8195 vppsys1 clock support
Add MT8195 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-22-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
f5bf0c1b48 clk: mediatek: Add MT8195 vppsys0 clock support
Add MT8195 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-21-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
b5d728d8f1 clk: mediatek: Add MT8195 vencsys clock support
Add MT8195 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:39 -07:00
Chun-Jie Chen
269987505b clk: mediatek: Add MT8195 vdosys1 clock support
Add MT8195 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
70282c90d4 clk: mediatek: Add MT8195 vdosys0 clock support
Add MT8195 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-18-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
d7338d06ac clk: mediatek: Add MT8195 vdecsys clock support
Add MT8195 vdec clock controllers which provide clock gate
control for video decoder.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-17-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
24da2c2429 clk: mediatek: Add MT8195 scp adsp clock support
Add MT8195 scp adsp clock controller which provides clock gate
control for Audio DSP.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
35016f10c0 clk: mediatek: Add MT8195 mfgcfg clock support
Add MT8195 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-15-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
d9943b6d71 clk: mediatek: Add MT8195 ipesys clock support
Add MT8195 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-14-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
9c4fec14ae clk: mediatek: Add MT8195 imgsys clock support
Add MT8195 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
7b2e1de8ae clk: mediatek: Add MT8195 ccusys clock support
Add MT8195 ccusys clock controller which provides clock gate
control in Camera Computing Unit.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-12-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:38 -07:00
Chun-Jie Chen
9d0c6572d5 clk: mediatek: Add MT8195 camsys clock support
Add MT8195 camsys clock controllers which provide clock gate
control for camera IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
e2edf59dec clk: mediatek: Add MT8195 infrastructure clock support
Add MT8195 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-10-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
a2a2c5fc5c clk: mediatek: Add MT8195 peripheral clock support
Add MT8195 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-9-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
0360be014c clk: mediatek: Add MT8195 topckgen clock support
Add MT8195 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-8-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
3e9121f16c clk: mediatek: Add MT8195 apmixedsys clock support
Add MT8195 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
6203815bf9 clk: mediatek: Fix resource leak in mtk_clk_simple_probe
Release clock data when clock driver probe fail to fix
possible resource leak.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-6-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
300796cad2 clk: mediatek: Add API for clock resource recycle
In order to avoid resource leak when fail clock registration appears,
so adds the common interface to handle it.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-5-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Chun-Jie Chen
cb95c169e9 clk: mediatek: Fix corner case of tuner_en_reg
On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-4-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 15:05:37 -07:00
Marijn Suijten
6d26bb22e9 clk: qcom: mmcc-msm8998: Remove unnecessary fallbacks to global clocks
A previous patch removes the "xo" clock from the global namespace making
it impossible to acquire by that ".name".  The device-tree for msm8998
currently does not include an mmcc node but the dt-bindings for this
compatible already require all these clocks, and the patch introducing
this node [1] also includes them.

[1]: https://patchwork.kernel.org/project/linux-arm-msm/patch/20210901183123.1087392-1-angelogioacchino.delregno@somainline.org/

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-9-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:33 -07:00
Marijn Suijten
7837187cb9 clk: qcom: gpucc-msm8998: Remove unnecessary fallbacks to global clocks
A previous patch removes the "xo" clock from the global namespace making
it impossible to acquire by that ".name".  The device-tree for msm8998
already provides the "xo" and "gpll0" clock since the addition of the
gpucc node making it unnecessary to have this fallback at all.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-8-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:33 -07:00
Marijn Suijten
9ee049ebb3 clk: qcom: mmcc-msm8998: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-6-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:32 -07:00
Marijn Suijten
ce336a51de clk: qcom: gpucc-msm8998: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-5-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:32 -07:00
Marijn Suijten
9d67de94e1 clk: qcom: gcc-msm8998: Remove transient global "xo" clock
Now that all clock controllers and the DSI PLL clocks rely on "xo" being
passed in DT as phandle instead of looking it up by the global "xo" name
this transient clock can be removed, leaving only the fixed-factor
"xo_board" clock in DT.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:32 -07:00
Marijn Suijten
e815e34b6b clk: qcom: gcc-msm8998: Use parent_data/hws for internal clock relations
Use parent_data and parent_hws to specify internal relations using
pointers instead of names, and use .fw_name to retrieve external clocks
from clock-names in the DT rather than the global clock tree.

Note that this change relies on the "xo" and "sleep_clk" clocks to be
provided in DT, as per the relevant qcom,gcc-mnsm8998.yaml dt-bindings.
These clocks have been added in a prior patch [1].

[1]: https://lore.kernel.org/linux-arm-msm/20210911120101.248476-1-marijn.suijten@somainline.org/

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-3-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:32 -07:00
Marijn Suijten
d6f1c681b7 clk: qcom: gcc-msm8998: Move parent names and mapping below GPLLs
Prepare for a future patch where we use .hw pointers to these GPLL
clocks in the parent mapping instead of name references.  This requires
the GPLL clocks to be decared before parent_data arrays.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:40:32 -07:00
Cai Huoqing
17c774ab41 clk: qcom: kpss-xcc: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084858.4101-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:39:44 -07:00
Cai Huoqing
437cbbb09b clk: qcom: common: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084851.4050-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:39:31 -07:00
Cai Huoqing
aacbbe6bdb clk: qcom: a53-pll: Make use of the helper function devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Link: https://lore.kernel.org/r/20210907084843.3999-1-caihuoqing@baidu.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:39:14 -07:00
Marijn Suijten
6e714b5838 clk: qcom: gpucc-sdm660: Remove fallback to global clock names
The necessary clocks for this driver are already fully specified in
sdm630 DT under the .fw_name, and do not need an implicit fallback to
their global name.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-5-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:09:48 -07:00
Marijn Suijten
916e9eceb0 clk: qcom: mmcc-sdm660: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:09:48 -07:00
Marijn Suijten
7340264ee4 clk: qcom: gpucc-sdm660: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-3-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:09:48 -07:00
Marijn Suijten
00ff818888 clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data instead of hardcoding a number that relies on an array
defined hundreds of lines above.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210829204822.289829-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14 14:09:47 -07:00
Cai Huoqing
1d26eaeec3 clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210907085122.4305-1-caihuoqing@baidu.com
2021-09-13 18:01:09 +02:00
Cai Huoqing
15b98bcae1 clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210907085115.4254-1-caihuoqing@baidu.com
2021-09-13 18:00:59 +02:00
Cai Huoqing
63b86b0155 clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210907085107.4203-1-caihuoqing@baidu.com
2021-09-13 18:00:51 +02:00
Cai Huoqing
c5c1a0ac6a clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
Use the devm_platform_ioremap_resource() helper instead of
calling platform_get_resource() and devm_ioremap_resource()
separately

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210907085100.4152-1-caihuoqing@baidu.com
2021-09-13 18:00:35 +02:00