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5 Commits

Author SHA1 Message Date
David S. Miller
b73d884756 sparc64: Initial niagara2 perf counter support. 
Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 07:42:02 -07:00
David S. Miller
660d13765f sparc64: Perf counter 'nop' event is not constant. 
On Niagara-2, for example, it's going to be different.  So make
it something specified in sparc_pmu.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 07:13:26 -07:00
David S. Miller
496c07e3b4 sparc64: Provide a way to specify a perf counter overflow IRQ enable bit. 
Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 07:10:59 -07:00
David S. Miller
91b9286d81 sparc64: Provide hypervisor tracing bit support for perf counters. 
A PMU need only specify which bit in the PCR enabled hypervisor
tracing in order to enable this.

This will be used in Niagara-2 perf counter support.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 07:09:06 -07:00
David S. Miller
59abbd1e7c sparc64: Initial hw perf counter support. 
Only supports one simple counter and only UltraSPARC-IIIi chips.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 06:28:20 -07:00