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4 Commits

Author SHA1 Message Date
John Crispin
37bcc03f97 MIPS: ralink: Fix invalid tick count 
The current code adds the delta twice, which is obviously wrong.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11443/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-11-11 08:38:04 +01:00
Viresh Kumar
59113d93c2 MIPS: rt3352: Migrate to new 'set-state' interface 
Migrate ralink driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-mips@linux-mips.org
Cc: linaro-kernel@lists.linaro.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Patchwork: https://patchwork.linux-mips.org/patch/10610/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-09-03 12:07:54 +02:00
Masanari Iida
77d84ff87e treewide: Fix typos in printk 
Correct spelling typo in various part of kernel

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
 2013-12-19 15:10:49 +01:00
John Crispin
1f2acc5a8a MIPS: ralink: Add support for systick timer found on newer ralink SoC 
Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent
of the SoC master clock. If we want to automatic frequency scaling to work we
need to use the systick timer as the clock source.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2013-09-04 16:55:29 +02:00