IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
Add support for the msm8916 BIMC (Bus Integrated Memory Controller)
clocks that are needed for GPU.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Some root clock generators may have child branches that are controlled
by different CPUs. These RCGs require some special operations:
- some enable bits have to be toggled when we set the rate;
- if RCG is disabled we only cache the rate and set it later when enabled;
- when the RCG is disabled, the mux is set to the safe source;
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
[sboyd@codeaurora.org: Simplify recalc_rate implementation]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for the msm8916 TCU (Translation Control Unit) clocks that
are needed for IOMMU.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There's just one GDSC as part of the msm8974 GCC block.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned
off.
The controls provided are granular enough to be able to support
various differnt levels of RET states, like a 'shallow RET' with all memory
retained and a 'deep RET' with some memory retained while some others
are lost. The current patch does not support this and considers
just one RET state where all memory is retained. Futher work, if
needed can support multiple different levels of RET state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sometimes the display driver may want to change the parent PLL of
the display clocks (byte and pixel clocks) depending on the
use-case. Currently the parent is fixed by means of having a
frequency table with one entry that chooses a particular parent.
Remove this restriction and use the parent the clock is
configured for in the hardware during clk_set_rate(). This
requires consumers to rely on the default parent or to configure
the parent with clk_set_parent()/assigned-clock-parents on the
clocks before calling clk_set_rate().
Tested-by: Archit Taneja <architt@codeaurora.org>
Cc: Hai Li <hali@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fix the enable bit of the pseudorandom number generator clock.
Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Fixes: 3966fab8b6 "clk: qcom: Add MSM8916 Global Clock Controller support"
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@
-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* cleanup-clk-h-includes: (62 commits)
clk: Remove clk.h from clk-provider.h
clk: h8300: Remove clk.h and clkdev.h includes
clk: at91: Include clk.h and slab.h
clk: ti: Switch clk-provider.h include to clk.h
clk: pistachio: Include clk.h
clk: ingenic: Include clk.h
clk: si570: Include clk.h
clk: moxart: Include clk.h
clk: cdce925: Include clk.h
clk: Include clk.h in clk.c
clk: zynq: Include clk.h
clk: ti: Include clk.h
clk: sunxi: Include clk.h and remove unused clkdev.h includes
clk: st: Include clk.h
clk: qcom: Include clk.h
clk: highbank: Include clk.h
clk: bcm: Include clk.h
clk: versatile: Remove clk.h and clkdev.h includes
clk: ux500: Remove clk.h and clkdev.h includes
clk: tegra: Properly include clk.h
...
The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.
Reported-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Tested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Fixes: 0282465320 ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.
Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.
The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for SR2 type pll operations. SR2 is optimized for Time Interval
Error (TIE) or absolute jitter.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Make const both the array and the strings, so they can be
moved to .rodata section.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
Signed-off-by: Hai Li <hali@codeaurora.org>
Tested-by: Archit Taneja <architt@codeaurora.org>
Fixes: 99cbd064b0 ("clk: qcom: Support display RCG clocks")
[sboyd@codeaurora.org: Silenced unused parent variable warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the NSS/GMAC clocks and the TCM clock and NSS resets.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
The gfx3d_clk_src parents configuration is incorrect. Fix it.
Fixes: 3966fab8b6 "clk: qcom: Add MSM8916 Global Clock Controller support"
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
One of the video codec clock frequencies has incorrect divider
value. Fix it.
Fixes: 3966fab8b6 "clk: qcom: Add MSM8916 Global Clock Controller support"
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
When we introduced the parent_map tables, we missed to update
some of the functions where mapping is translated. Fix this.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Support for Qualcomm's clock controllers should be available only
on Qualcomm platforms.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The NAND controller within EBI2 requires EBI2_CLK and
EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so
that they can be used by the NAND controller driver. Add an entry
for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/clk-pll.c:74:1-4: WARNING: end returns can be simpified
Simplify a trivial if-return sequence. Possibly combine with a
preceding function call.
Generated by: scripts/coccinelle/misc/simple_return.cocci
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These frequency tables list the wrong rates. Either they don't
have the correct frequency at all, or they're specified in kHz
instead of Hz. Fix it.
Fixes: c99e515a92 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe and control
their clocks and resets.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
[sboyd@codeaurora.org: Removed NULL entry from parent_maps]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.
This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
- Define a parent_map struct to map the relations between PLL source index
and register configuration value.
- Add a qcom_find_src_index() function for finding the index of a clock
matching the specific PLL configuration.
- Update the {set,get}_parent RCG functions use the newly introduced
parent_map struct.
- Convert all existing drivers to the new parent_map tables.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently configure_bank() returns void. Add some error
checking on the regmap calls and propagate if there is
any error.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
According to the common clock framework API, the clk_get_parent() function
should return u8. Currently we are returning negative values on error. Fix
this and use the default parent in case of an error.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.
In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.
Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Fixes: bcd61c0f53 (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ahbix clock can never be turned off in practice. To change the
rates we need to switch the mux off the M/N counter to an always on
source (XO), reprogram the M/N counter to get the rate we want and
finally switch back to the M/N counter. Add a new ops structure
for this type of clock so that we can set the rate properly.
Fixes: c99e515a92 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
PXO is 25MHz, not 27MHz. Fix the table.
Fixes: 24d8fba44a "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <agross@codeaurora.org>
Tested-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
drivers/clk/qcom/lcc-msm8960.c:577:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This clock is needed for most audio clock frequencies. Add it.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
regmap_read() returns 0 on success, not the value of the register
that is read. Fix it so we properly detect the frequency plan.
Fixes: b82875ee07 "clk: qcom: Add MSM8960/APQ8064 LPASS clock
controller (LCC) driver"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
These shifts were copy/pasted from the pcm which is a different
size RCG. Use the correct offsets so that slimbus rates are
correct.
Fixes: b82875ee07 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.
Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
migrated clk-private.h changes to clk.c]
