6bdfd9f118
perf jevents: Fix period for Intel fixed counters
...
The Intel fixed counters use a special table to override the JSON
information.
During this override the period information from the JSON file got
dropped, which results in inst_retired.any and similar running with
frequency mode instead of a period.
Just specify the expected period in the table.
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: http://lore.kernel.org/lkml/20190927233546.11533-2-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-30 17:29:53 -03:00
0d0e5ecec6
perf vendor events s390: Use s390 machine name instead of type 8561
...
In the pmu-events directory for JSON file definitions use the
official machine name IBM z15 instead of machine type number
8561. This is consistent with previous machines.
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com >
Cc: Heiko Carstens <heiko.carstens@de.ibm.com >
Cc: Vasily Gorbik <gor@linux.ibm.com >
Link: http://lore.kernel.org/lkml/20190927081147.18345-2-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-30 17:29:45 -03:00
02d0847922
perf vendor events s390: Add JSON transaction for machine type 8561
...
Add s390 transaction counter definition for machine 8561. This is the
same file as for the predecessor machine.
Fixes: 6e67d77d67tmricht@linux.ibm.com >
Cc: Heiko Carstens <heiko.carstens@de.ibm.com >
Cc: Vasily Gorbik <gor@linux.ibm.com >
Link: http://lore.kernel.org/lkml/20190927081147.18345-1-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-30 17:29:42 -03:00
28b951760c
perf vendor events: Remove P8 HW events which are not supported
...
This patch is to remove following hardware events
from JSON file which are not supported on POWER8.
pm_l3_p0_grp_pump
pm_l3_p0_lco_data
pm_l3_p0_lco_no_data
pm_l3_p0_lco_rty
Note: Unfortunately power8 event list is not publicly available.
Fixes: c3b4d5c4afmamatha4@linux.vnet.ibm.com >
Acked-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lore.kernel.org/lkml/20190909065624.11956.3992.stgit@localhost.localdomain
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-25 16:26:40 -03:00
93125562ce
perf vendor events: Minor fixes to the README
...
Some grammatical fixes, and updates to some path references that have
since changed.
Signed-off-by: Kim Phillips <kim.phillips@amd.com >
Reviewed-by: Andi Kleen <ak@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Borislav Petkov <bp@suse.de >
Cc: Janakarajan Natarajan <janakarajan.natarajan@amd.com >
Cc: Jin Yao <yao.jin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Luke Mujica <lukemujica@google.com >
Cc: Martin Liška <mliska@suse.cz >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lore.kernel.org/lkml/20190919204306.12598-3-kim.phillips@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-25 09:51:42 -03:00
0c03d3aa25
perf vendor events amd: Remove redundant '['
...
Remove the redundant '['.
'perf list' output before:
ex_ret_brn
[[Retired Branch Instructions]
'perf list' output after:
ex_ret_brn
[Retired Branch Instructions]
Fixes: 98c07a8f74kim.phillips@amd.com >
Reviewed-by: Andi Kleen <ak@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Borislav Petkov <bp@suse.de >
Cc: Janakarajan Natarajan <janakarajan.natarajan@amd.com >
Cc: Jin Yao <yao.jin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Luke Mujica <lukemujica@google.com >
Cc: Martin Liška <mliska@suse.cz >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lore.kernel.org/lkml/20190919204306.12598-2-kim.phillips@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-25 09:51:42 -03:00
faef874941
perf vendor events amd: Add L3 cache events for Family 17h
...
Allow users to symbolically specify L3 events for Family 17h processors
using the existing AMD Uncore driver.
Source of events descriptions are from section 2.1.15.4.1 "L3 Cache PMC
Events" of the latest Family 17h PPR, available here:
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Opnly BriefDescriptions added, since they show with and without
the -v and --details flags.
Tested with:
# perf stat -e l3_request_g1.caching_l3_cache_accesses,amd_l3/event=0x01,umask=0x80/,l3_comb_clstr_state.request_miss,amd_l3/event=0x06,umask=0x01/ perf bench mem memcpy -s 4mb -l 100 -f default
...
7,006,831 l3_request_g1.caching_l3_cache_accesses
7,006,830 amd_l3/event=0x01,umask=0x80/
366,530 l3_comb_clstr_state.request_miss
366,568 amd_l3/event=0x06,umask=0x01/
Signed-off-by: Kim Phillips <kim.phillips@amd.com >
Reviewed-by: Andi Kleen <ak@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Borislav Petkov <bp@suse.de >
Cc: Janakarajan Natarajan <janakarajan.natarajan@amd.com >
Cc: Jin Yao <yao.jin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Luke Mujica <lukemujica@google.com >
Cc: Martin Liška <mliska@suse.cz >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lore.kernel.org/lkml/20190919204306.12598-1-kim.phillips@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-25 09:51:35 -03:00
9e282b7394
perf tools: Add PMU event JSON files for ARM Cortex-A76 and, Neoverse N1.
...
The source of the event codes and description text was the Neoverse N1
technical reference manual at:
http://infocenter.arm.com/help/topic/com.arm.doc.100616_0301_01_en/neoverse_n1_trm_100616_0301_01_en.pdf
The Cortex-A76 shares the same event IDs as the Neoverse N1 and they
can be viewed at:
https://static.docs.arm.com/100798/0400/cortex_a76_trm_100798_0400_00_en.pdf
Signed-off-by: James Clark <james.clark@arm.com >
Cc: "linux-perf-users@vger.kernel.org " <linux-perf-users@vger.kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Jeremy Linton <jeremy.linton@arm.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Suzuki Poulouse <suzuki.poulose@arm.com >
Cc: james clark <james.clark@arm.com >
Cc: nd <nd@arm.com >
Link: http://lore.kernel.org/lkml/20190902160713.1425-2-james.clark@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-09-20 09:19:20 -03:00
11e54d35e6
perf vendor events intel: Add Tremontx event file v1.02
...
Add a Intel event file for perf.
Signed-off-by: Haiyan Song <haiyanx.song@intel.com >
Reviewed-by: Kan Liang <kan.liang@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Jin Yao <yao.jin@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lkml.kernel.org/r/20190815035942.30602-1-haiyanx.song@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-08-15 12:04:04 -03:00
b115df076d
perf vendor events intel: Add Icelake V1.00 event file
...
Add a Intel event file for perf.
Signed-off-by: Haiyan Song <haiyanx.song@intel.com >
Reviewed-by: Kan Liang <kan.liang@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Jin Yao <yao.jin@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: https://lkml.kernel.org/r/8859095e-5b02-d6b7-fbdc-3f42b714bae0@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-08-12 16:26:02 -03:00
272172bd41
Merge remote-tracking branch 'torvalds/master' into perf/core
...
To get closer to upstream and check if we need to sync more UAPI
headers, pick up fixes for libbpf that prevent perf's container tests
from completing successfuly, etc.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-08-12 16:25:00 -03:00
8e6e5bea2e
perf pmu-events: Fix missing "cpu_clk_unhalted.core" event
...
The events defined in pmu-events JSON are parsed and added into perf
tool. For fixed counters, we handle the encodings between JSON and perf
by using a static array fixed[].
But the fixed[] has missed an important event "cpu_clk_unhalted.core".
For example, on the Tremont platform,
[root@localhost ~]# perf stat -e cpu_clk_unhalted.core -a
event syntax error: 'cpu_clk_unhalted.core'
\___ parser error
With this patch, the event cpu_clk_unhalted.core can be parsed.
[root@localhost perf]# ./perf stat -e cpu_clk_unhalted.core -a -vvv
------------------------------------------------------------
perf_event_attr:
type 4
size 112
config 0x3c
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
...
Signed-off-by: Jin Yao <yao.jin@linux.intel.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Jin Yao <yao.jin@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Peter Zijlstra <peterz@infradead.org >
Link: http://lkml.kernel.org/r/20190729072755.2166-1-yao.jin@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-08-08 15:41:37 -03:00
123a039d0d
perf vendor events power9: Added missing event descriptions
...
Documentation source:
https://wiki.raptorcs.com/w/images/6/6b/POWER9_PMU_UG_v12_28NOV2018_pub.pdf
Signed-off-by: Michael Petlan <mpetlan@redhat.com >
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Paul Clarke <pc@us.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Cc: linuxppc-dev@ozlabs.org
LPU-Reference: 20190719100837.7503-1-mpetlan@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-29 18:34:47 -03:00
6e67d77d67
perf vendor events s390: Add JSON files for machine type 8561
...
Add CPU measurement counter facility event description files (JSON) for
IBM machine types 8561 and 8562.
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com >
Reviewed-by: Vasily Gorbik <gor@linux.ibm.com >
Cc: Heiko Carstens <heiko.carstens@de.ibm.com >
Cc: Hendrik Brueckner <brueckner@linux.ibm.com >
Link: http://lkml.kernel.org/r/20190712123113.100882-1-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-12 13:51:59 -03:00
e56fbc9dc7
perf tools: Use list_del_init() more thorougly
...
To allow for destructors to check if they're operating on a object still
in a list, and to avoid going from use after free list entries into
still valid, or even also other already removed from list entries.
Cc: Adrian Hunter <adrian.hunter@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Link: https://lkml.kernel.org/n/tip-deh17ub44atyox3j90e6rksu@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-09 10:13:27 -03:00
4df79ba3eb
perf vendor events intel: Metric fixes for SKX/CLX
...
- Add a missing filter for the DRAM_Latency / DRAM_Parallel_Reads metrics
- Remove the useless PMM_* metrics from Skylake
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: http://lkml.kernel.org/r/20190628220737.13259-1-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-02 16:08:16 -03:00
edd93a4076
perf jevents: Add support for Hisi hip08 L3C PMU aliasing
...
Add support for Hisi hip08 L3C PMU aliasing.
The kernel driver is in drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
Signed-off-by: John Garry <john.garry@huawei.com >
Acked-by: Jiri Olsa <jolsa@kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Ben Hutchings <ben@decadent.org.uk >
Cc: Hendrik Brueckner <brueckner@linux.ibm.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com >
Cc: Thomas Richter <tmricht@linux.ibm.com >
Cc: Will Deacon <will.deacon@arm.com >
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1561732552-143038-5-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-02 16:08:16 -03:00
8f5b703add
perf jevents: Add support for Hisi hip08 HHA PMU aliasing
...
Add support for Hisi hip08 HHA PMU aliasing.
The kernel driver is in drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
Signed-off-by: John Garry <john.garry@huawei.com >
Acked-by: Jiri Olsa <jolsa@kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Ben Hutchings <ben@decadent.org.uk >
Cc: Hendrik Brueckner <brueckner@linux.ibm.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com >
Cc: Thomas Richter <tmricht@linux.ibm.com >
Cc: Will Deacon <will.deacon@arm.com >
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1561732552-143038-4-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-02 16:08:15 -03:00
57cc732479
perf jevents: Add support for Hisi hip08 DDRC PMU aliasing
...
Add support for Hisi hip08 DDRC PMU aliasing. We can now do something like
this:
$perf list
[snip]
uncore ddrc:
uncore_hisi_ddrc.act_cmd
[DDRC active commands. Unit: hisi_sccl,ddrc]
uncore_hisi_ddrc.flux_rcmd
[DDRC read commands. Unit: hisi_sccl,ddrc]
uncore_hisi_ddrc.flux_wcmd
[DDRC write commands. Unit: hisi_sccl,ddrc]
uncore_hisi_ddrc.flux_wr
[DDRC precharge commands. Unit: hisi_sccl,ddrc]
uncore_hisi_ddrc.rnk_chg
[DDRC rank commands. Unit: hisi_sccl,ddrc]
uncore_hisi_ddrc.rw_chg
[DDRC read and write changes. Unit: hisi_sccl,ddrc]
Performance counter stats for 'system wide':
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl1_ddrc0]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl3_ddrc1]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl5_ddrc2]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl7_ddrc3]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl5_ddrc0]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl7_ddrc1]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl1_ddrc3]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl1_ddrc1]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl3_ddrc2]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl5_ddrc3]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl3_ddrc0]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl5_ddrc1]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl7_ddrc2]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl7_ddrc0]
20,421 uncore_hisi_ddrc.flux_rcmd [hisi_sccl1_ddrc2]
0 uncore_hisi_ddrc.flux_rcmd [hisi_sccl3_ddrc3]
1.001559011 seconds time elapsed
The kernel driver is in drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
Signed-off-by: John Garry <john.garry@huawei.com >
Acked-by: Jiri Olsa <jolsa@kernel.org >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Ben Hutchings <ben@decadent.org.uk >
Cc: Hendrik Brueckner <brueckner@linux.ibm.com >
Cc: Kan Liang <kan.liang@linux.intel.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Mathieu Poirier <mathieu.poirier@linaro.org >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com >
Cc: Thomas Richter <tmricht@linux.ibm.com >
Cc: Will Deacon <will.deacon@arm.com >
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1561732552-143038-3-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-02 16:08:15 -03:00
06c642c0e9
perf jevents: Use nonlocal include statements in pmu-events.c
...
Change pmu-events.c to not use local include statements. The code that
creates the include statements for pmu-events.c is in jevents.c.
pmu-events.c is a generated file, and for build systems that put
generated files in a separate directory, include statements with local
pathing cannot find non-generated files.
Signed-off-by: Luke Mujica <lukemujica@google.com >
Cc: Ian Rogers <irogers@google.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Numfor Mbiziwo-Tiapo <nums@google.com >
Cc: Stephane Eranian <eranian@google.com >
Link: https://lkml.kernel.org/n/tip-prgnwmaoo1pv9zz4vnv1bjaj@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-07-01 22:50:42 -03:00
7025fdbea3
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
...
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com >
Reviewed-by: John Garry <john.garry@huawei.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Catalin Marinas <catalin.marinas@arm.com >
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Sean V Kelley <seanvk.dev@oregontracks.org >
Cc: Will Deacon <will.deacon@arm.com >
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-05-15 16:36:49 -03:00
93fe8f1e11
perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
...
Broadcom's Brahma-B53 CPUs support the same type of events that the
Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53
events.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com >
Acked-by: Will Deacon <will.deacon@arm.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Catalin Marinas <catalin.marinas@arm.com >
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Sean V Kelley <seanvk.dev@oregontracks.org >
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org (moderated list
Link: http://lkml.kernel.org/r/20190513202522.9050-3-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-05-15 16:36:49 -03:00
ae833a6124
perf vendor events arm64: Remove [[:xdigit:]] wildcard
...
ARM64's implementation of get_cpuidr_str() masks out the revision bits
[3:0] while reading the CPU identifier, there is no need for the
[[:xdigit:]] wildcard.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Catalin Marinas <catalin.marinas@arm.com >
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Mark Rutland <mark.rutland@arm.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Sean V Kelley <seanvk.dev@oregontracks.org >
Cc: Will Deacon <will.deacon@arm.com >
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190513202522.9050-2-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-05-15 16:36:49 -03:00
8e8f515d56
perf jevents: Remove unused variable
...
Address gcc warning:
pmu-events/jevents.c: In function ‘save_arch_std_events’:
pmu-events/jevents.c:417:15: warning: unused variable ‘sb’ [-Wunused-variable]
struct stat *sb = data;
^~
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: John Garry <john.garry@huawei.com >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: wanghaibin.wang@huawei.com
Link: http://lkml.kernel.org/r/1557919169-23972-1-git-send-email-yuzenghui@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-05-15 16:36:49 -03:00
bf6d18cffa
perf vendor events intel: Add uncore_upi JSON support
...
Perf cannot parse UPI (Intel's "Ultra Path Interconnect" [1]) events.
# perf stat -e UPI_DATA_BANDWIDTH_TX
event syntax error: 'UPI_DATA_BANDWIDTH_TX'
\___ parser error
Run 'perf list' for a list of valid events
The JSON lists call the box UPI LL, while perf calls it upi. Add
conversion support to JSON to convert the unit properly.
Committer notes:
[1] https://en.wikipedia.org/wiki/Intel_Ultra_Path_Interconnect
"The Intel Ultra Path Interconnect (UPI) is a point-to-point processor
interconnect developed by Intel which replaced the Intel QuickPath
Interconnect (QPI) in Xeon Skylake-SP platforms starting in 2017.
UPI is a low-latency coherent interconnect for scalable multiprocessor
systems with a shared address space. It uses a directory-based home
snoop coherency protocol with a transfer speed of up to 10.4 GT/s.
Supporting processors typically have two or three UPI links."
Signed-off-by: Kan Liang <kan.liang@linux.intel.com >
Cc: Andi Kleen <ak@linux.intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: http://lkml.kernel.org/r/1557234991-130456-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-05-15 16:36:47 -03:00
1c3a2c864d
perf vendor events intel: Update Silvermont to v14
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:48 -03:00
c53dd58988
perf vendor events intel: Update GoldmontPlus to v1.01
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:46 -03:00
f3ef08583e
perf vendor events intel: Update Goldmont to v13
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:44 -03:00
b1580f542c
perf vendor events intel: Update Bonnell to V4
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:42 -03:00
643e72255e
perf vendor events intel: Update KnightsLanding events to v9
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:40 -03:00
efc351f1b5
perf vendor events intel: Update Haswell events to v28
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:38 -03:00
2111da70ff
perf vendor events intel: Update IvyBridge events to v21
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:35 -03:00
59da390e54
perf vendor events intel: Update SandyBridge events to v16
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:33 -03:00
e6b32be445
perf vendor events intel: Update JakeTown events to v20
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:31 -03:00
009edd9ae0
perf vendor events intel: Update IvyTown events to v20
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:29 -03:00
e313477f7e
perf vendor events intel: Update HaswellX events to v20
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:26 -03:00
9f0f4a242c
perf vendor events intel: Update BroadwellX events to v14
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:24 -03:00
19f2d40c57
perf vendor events intel: Update SkylakeX events to v1.12
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:21 -03:00
24339348b9
perf vendor events intel: Update Skylake events to v42
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:18 -03:00
d2243329ef
perf vendor events intel: Update Broadwell-DE events to v7
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:14 -03:00
8313fe2d68
perf vendor events intel: Update Broadwell events to v23
...
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:23:09 -03:00
fd5500989c
perf vendor events intel: Update metrics from TMAM 3.5
...
Update all the Intel JSON metrics from Ahmad Yasin's TMAM 3.5
for Intel big core from Sandy Bridge to Cascade Lake.
This has many improvements and new metircs
- New TopDownL1_SMT group that provides a per SMT thread version
of --topdown that does not require -a anymore. The drawback is
increased multiplexing though since L1 TopDown does not fit into
4 generic counters anymore.
- Added SMT aware versions of other metrics
- Split SMT aware metrics into separate metrics to avoid
unnecessary event collections
- New metrics for better branch analysis:
Estimated Branch_Mispredict_Costs, Instructions per taken Branch,
Branch Instructions per Taken Branch, etc.
- Instruction mix metrics:
Instructions per load, Instructions per store, Instructions per Branch,
Instructions per Call
- New Cache metrics:
Bandwidth to L1/L2/L3 caches. L1/L2/L3 misses per kilo instructions.
memory level parallelism
- New memory controller metrics:
Normalized memory bandwidth in interval mode, Average memory latency,
Average number of parallel read requests,
- 3DXP persistent memory metrics for Cascade Lake:
3dxp read latency, 3dxp read/write bandwidth
- Some other useful metrics like Instruction Level Parallelism,
- Various other improvements.
Not all metrics are available on all CPUs. Skylake has best coverage.
Signed-off-by: Andi Kleen <ak@linux.intel.com >
Cc: Kan Liang <kan.liang@intel.com >
Cc: Jiri Olsa <jolsa@kernel.org >
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 15:22:22 -03:00
7fcfa9a2d9
perf list: Fix s390 counter long description for L1D_RO_EXCL_WRITES
...
Command
# perf list --long-desc pmu
lists the long description of the available counters. For counter
named L1D_RO_EXCL_WRITES on machine types 3906 and 3907 the long
description contains the counter number 'Counter:128 Name:'
prefix. This is wrong.
The fix changes the description text and removes this prefix.
Output before:
[root@m35lp76 perf]# ./perf list --long-desc pmu
...
L1D_ONDRAWER_L4_SOURCED_WRITES
[A directory write to the Level-1 Data cache directory where the
returned cache line was sourced from On-Drawer Level-4 cache]
L1D_RO_EXCL_WRITES
[Counter:128 Name:L1D_RO_EXCL_WRITES A directory write to the Level-1
Data cache where the line was originally in a Read-Only state in the
cache but has been updated to be in the Exclusive state that allows
stores to the cache line]
...
Output after:
[root@m35lp76 perf]# ./perf list --long-desc pmu
...
L1D_ONDRAWER_L4_SOURCED_WRITES
[A directory write to the Level-1 Data cache directory where the
returned cache line was sourced from On-Drawer Level-4 cache]
L1D_RO_EXCL_WRITES
[L1D_RO_EXCL_WRITES A directory write to the Level-1
Data cache where the line was originally in a Read-Only state in the
cache but has been updated to be in the Exclusive state that allows
stores to the cache line]
...
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com >
Cc: Heiko Carstens <heiko.carstens@de.ibm.com >
Cc: Hendrik Brueckner <brueckner@linux.vnet.ibm.com >
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com >
Fixes: 109d59b900http://lkml.kernel.org/r/20190329133337.60255-1-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-04-01 14:49:24 -03:00
c3b4d5c4af
perf vendor events: Remove P8 HW events which are not supported
...
This patch is to remove following hardware events from JSON file which
are not supported on POWER8.
pm_co_disp_fail
pm_co_tm_sc_footprint
pm_iside_disp
pm_iside_disp_fail
pm_iside_disp_fail_other
pm_iside_mru_touch
pm_l2_castout_mod
pm_l2_castout_shr
pm_l2_dc_inv
pm_l2_disp_all_l2miss
pm_l2_grp_guess_correct
pm_l2_grp_guess_wrong
pm_l2_ic_inv
pm_l2_inst
pm_l2_inst_miss
pm_l2_ld
pm_l2_ld_disp
pm_l2_ld_hit
pm_l2_ld_miss
pm_l2_loc_guess_correct
pm_l2_loc_guess_wrong
pm_l2_rcld_disp
pm_l2_rcld_disp_fail_addr
pm_l2_rcld_disp_fail_other
pm_l2_rcst_disp
pm_l2_rcst_disp_fail_addr
pm_l2_rcst_disp_fail_other
pm_l2_rc_st_done
pm_l2_rty_ld
pm_l2_sn_m_rd_done
pm_l2_sn_m_wr_done
pm_l2_sn_sx_i_done
pm_l2_st_disp
pm_l2_st_hit
pm_l2_sys_guess_correct
pm_l2_sys_guess_wrong
pm_l2_sys_pump
pm_l3_ci_hit
pm_l3_ci_miss
pm_l3_cinj
pm_l3_co
pm_l3_co_lco
pm_l3_grp_guess_correct
pm_l3_grp_guess_wrong_high
pm_l3_grp_guess_wrong_low
pm_l3_hit
pm_l3_l2_co_hit
pm_l3_l2_co_miss
pm_l3_lat_ci_hit
pm_l3_lat_ci_miss
pm_l3_ld_hit
pm_l3_ld_miss
pm_l3_loc_guess_correct
pm_l3_loc_guess_wrong
pm_l3_miss
pm_l3_p0_co_l31
pm_l3_p0_co_mem
pm_l3_p0_co_rty
pm_l3_p0_grp_pump
pm_l3_p0_lco_data
pm_l3_p0_lco_no_data
pm_l3_p0_lco_rty
pm_l3_p0_node_pump
pm_l3_p0_pf_rty
pm_l3_p0_sn_hit
pm_l3_p0_sn_inv
pm_l3_p0_sn_miss
pm_l3_p0_sys_pump
pm_l3_p1_co_l31
pm_l3_p1_co_mem
pm_l3_p1_co_rty
pm_l3_p1_grp_pump
pm_l3_p1_lco_data
pm_l3_p1_lco_no_data
pm_l3_p1_lco_rty
pm_l3_p1_node_pump
pm_l3_p1_pf_rty
pm_l3_p1_sn_hit
pm_l3_p1_sn_inv
pm_l3_p1_sn_miss
pm_l3_p1_sys_pump
pm_l3_pf_hit_l3
pm_l3_sys_guess_correct
pm_l3_sys_guess_wrong
pm_l3_trans_pf
pm_l3_wi0_busy
pm_l3_wi_usage
pm_non_tm_rst_sc
pm_rd_clearing_sc
pm_rd_forming_sc
pm_rd_hit_pf
pm_snp_tm_hit_m
pm_snp_tm_hit_t
pm_st_caused_fail
pm_tm_cam_overflow
pm_tm_cap_overflow
pm_tm_fav_caused_fail
pm_tm_ld_caused_fail
pm_tm_ld_conf
pm_tm_rst_sc
pm_tm_sc_co
pm_tm_st_caused_fail
pm_tm_st_conf
Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com >
Acked-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com >
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Namhyung Kim <namhyung@kernel.org >
Cc: Peter Zijlstra <peterz@infradead.org >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Fixes: 2a81fa3bb5http://lkml.kernel.org/r/154953186583.11022.14819560028300370163.stgit@localhost.localdomain
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-03-19 16:52:03 -03:00
98c07a8f74
perf vendor events amd: perf PMU events for AMD Family 17h
...
Thi patch adds PMC events for AMD Family 17 CPUs as defined in [1]. It
covers events described in section: 2.1.13. Regex pattern in mapfile.csv
covers all CPUs of the family.
[1] https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
Signed-off-by: Martin Liška <mliska@suse.cz >
Acked-by: Borislav Petkov <bp@suse.de >
Cc: Jiri Olsa <jolsa@redhat.com >
Cc: Jon Grimm <jon.grimm@amd.com >
Cc: Martin Jambor <mjambor@suse.cz >
Cc: William Cohen <wcohen@redhat.com >
Link: https://lkml.kernel.org/r/d65873ca-e402-b198-4fe9-8c4af81258c8@suse.cz
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-03-11 11:56:03 -03:00
33937e5994
perf vendor events power9: General metrics
...
Descriptions of metrics for POWER9 processors can be found in the
"POWER9 Performance Monitor Unit User’s Guide", which is currently
available on the "IBM Portal for OpenPOWER"
(https://www-355.ibm.com/systems/power/openpower/welcome.xhtml ) at
https://www-355.ibm.com/systems/power/openpower/posting.xhtml?postingId=4948CDE1963C9BCA852582F800718190
This patch is for metric groups:
- general
and other metrics not in a metric group.
Signed-off-by: Paul Clarke <pc@us.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Cc: linuxppc-dev@ozlabs.org
Link: http://lkml.kernel.org/r/20190209181429.23950-5-pc@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-02-14 13:31:11 -03:00
a4d8327264
perf vendor events power9: Branch_prediction, instruction_stats, latency, lsu_rejects, memory, prefetch & translation metrics
...
Descriptions of metrics for POWER9 processors can be found in the
"POWER9 Performance Monitor Unit User’s Guide", which is currently
available on the "IBM Portal for OpenPOWER"
(https://www-355.ibm.com/systems/power/openpower/welcome.xhtml ) at
https://www-355.ibm.com/systems/power/openpower/posting.xhtml?postingId=4948CDE1963C9BCA852582F800718190
This patch is for metric groups:
- branch_prediction
- instruction_stats_percent_per_ref
- latency
- lsu_rejects
- memory
- prefetch
- translation
Plus, some whitespace changes.
Signed-off-by: Paul Clarke <pc@us.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Cc: linuxppc-dev@ozlabs.org
Link: http://lkml.kernel.org/r/20190209181429.23950-4-pc@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-02-14 13:31:10 -03:00
0133491d46
perf vendor events power9: Dl1_reloads, instruction_misses, l[23]_stats & pteg_reloads metrics
...
Descriptions of metrics for POWER9 processors can be found in the
"POWER9 Performance Monitor Unit User’s Guide", which is currently
available on the "IBM Portal for OpenPOWER"
(https://www-355.ibm.com/systems/power/openpower/welcome.xhtml ) at
https://www-355.ibm.com/systems/power/openpower/posting.xhtml?postingId=4948CDE1963C9BCA852582F800718190
This patch is for metric groups:
- dl1_reloads_percent_per_inst
- dl1_reloads_percent_per_ref
- instruction_misses_percent_per_inst
- l2_stats
- l3_stats
- pteg_reloads_percent_per_inst
- pteg_reloads_percent_per_ref
Signed-off-by: Paul Clarke <pc@us.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Cc: linuxppc-dev@ozlabs.org
Link: http://lkml.kernel.org/r/20190209181429.23950-3-pc@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-02-14 13:31:10 -03:00
7f3cf5ac77
perf vendor events power9: Cpi_breakdown & estimated_dcache_miss_cpi metrics
...
Descriptions of metrics for POWER9 processors can be found in the
"POWER9 Performance Monitor Unit User’s Guide", which is currently
available on the "IBM Portal for OpenPOWER"
(https://www-355.ibm.com/systems/power/openpower/welcome.xhtml ) at
https://www-355.ibm.com/systems/power/openpower/posting.xhtml?postingId=4948CDE1963C9BCA852582F800718190
This patch is for metric groups:
- cpi_breakdown
- estimated_dcache_miss_cpi
Signed-off-by: Paul Clarke <pc@us.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Cc: linuxppc-dev@ozlabs.org
Link: http://lkml.kernel.org/r/20190209181429.23950-2-pc@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-02-14 13:31:10 -03:00
72ab50203f
perf vendor events power8: Translaton & general metrics
...
POWER8 metrics are not well publicized.
Some are here:
https://www.ibm.com/support/knowledgecenter/en/SSFK5S_2.2.0/com.ibm.cluster.pedev.v2r2.pedev100.doc/bl7ug_derivedmetricspower8.htm
This patch is for metric groups:
- translation
- general
and other metrics not in a metric group.
Signed-off-by: Paul Clarke <pc@us.ibm.com >
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com >
Cc: Carl Love <cel@us.ibm.com >
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com >
Cc: Michael Ellerman <mpe@ellerman.id.au >
Cc: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com >
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com >
Link: http://lkml.kernel.org/r/20190207175314.31813-5-pc@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com >
2019-02-14 13:31:10 -03:00
