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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
losing clock configuration. Hence add a notifier chain that can be used
by core clocks to save/restore clock state during system suspend/resume.
The implementation of the actual clock state save/restore operations is
clock-specific, and to be registered with the notifier chain in the SoC
or family-specific cpg_mssr_info.cpg_clk_register() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module
Standby and Software Reset support code, using the CPG/MSSR driver
core.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
