IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.
Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.
Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The CPU clock defined in the Meson GX clock driver is actually a
left-over from the Meson8b clock controller. Un-export the clock so we
can remove it from the driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the clock ids of the three none AO uarts to the dt-bindings
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy the commit message to match similar change]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the SPICC gate clock to enable the SPICC controller.
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy commit message to match similar changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the spdif master clock and the mux to select the appropriate spdif
clock parent depending on the data source.
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the clock gates required for the spdif output
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add new flags to allow users to specify that they are not concerned with
the status of GPIOs whilst in a sleep/low power state.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the DT binding macros used by the reset controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds scpsys support for MT6797
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add the bit locations that correspond to the USB clocks.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the GyroADC clock to the R8A7791 device tree.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
to me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core, mostly
small non-critical fixes here and there as well as driver updates for new
and existing hardware support. The biggest things are the TI clk driver
rework to lay the groundwork for clkctrl support in the next merge window
and the AmLogic audio/graphics clk support.
Core:
* clk_possible_parents debugfs file so we know which parents a clk
could possibly have
* Fix to make clk rate change notifiers stop on the first failure instead
of continuing
New Drivers:
* Mediatek MT6797 SoCs
* hi655x PMIC clks
* AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
* Allwinner H5 SoCs and PRCM hardware
Updates:
* Nvidia Tegra T210 cleanups and non-critical fixes
* TI OMAP cleanups in preparation for clkctrl support
* Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
* ZTE zx296718 SoC VGA clks
* Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
* Support for IDT VersaClock 5P49V5935
* Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJZE0YJAAoJEK0CiJfG5JUl9tEQAKVJx8VztYGt1REoFMtEEHmO
azhxT/uYGgdOMAr9a3mQxqfm5cJbjnb1EZj2RfC1XHs31BF66j40y9+5d8hY8Hzu
5IkY86s77TlqxGLwQcAsU75Q9cFrEW9X0KJ6OSzlrcc5hKlAEk/Z5lBKoQAm3mlU
JqD4DSyFqP0X3YSxV5R7yfarb/X3ekCiQ13EDrPRRhyvHUi6ReUJDDgbPHtA+O2c
ftLAARmxjzitzyvdXokXudkfNm8F5KePK+QkVikf6D/q+kx1D0BNJwZIjhpoiksn
z6LImLQ8l91AWghmqqpOFXolxQncPU+bJIL9Pox76p5b3EzbQuthIafiso8KsDST
4g3mHm42Yfx9uoF+U+pR8IeZfj5yQT91bvf8naPz/ngWMAlLP1IKJUvJN6jeTiwe
cO6GIec1OH40Xl7v/9EafMwDcnFG0cwQmzr/M6wi1dUlmbSygP9NOMTHlr6W/0wa
K2hCD6b5UHEgHmdfiJbZ2tKxLO0e8LABW+AU8fQH5S2eNe14vY0GvCzfAq5MArIz
QRpso/kdtGpTpwMEvV6PUmJ0IxYEjtNJVjGJYbORwios0SK0Xl6bJWf7gwn5crB6
nua9tVZtJEOHJS7S+ESp3VvuXj2/UGPoRRf5OsERo1S6ydGUQH+wDi1SJMdo/vtX
bIPzIw6WPxMp24JyKOhh
=/5a/
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
changes, but also some new platforms that are worth mentioning:
* Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
Plus (Kevin)
* Orange Pi PC2 (Allwinner H5)
* Freescale LS2088A and LS1088A SoCs
* Expanded support for Nvidia Tegra186 (and Jetson TX2)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZEA5TAAoJEIwa5zzehBx3uPwP/3NBPKvsDQha/x+PPgtSM1cM
pUEF1fxsLftrt+pUeRgMZqGE2xu5vVUKEQsr7KDdWMS9LMs50Pp9dTvfxr7A4Asm
WRRMR7Y3gPbr49uf4+JLLmn0hYXTeaoUftVneBj0qU9Flwe3mQDVULiRjPalWYVB
g0+NwkPE2lrqrudceA2HiVEXqNlVXCIh2mdMaC7Luo0VEsz7nRHT0TOGPaxnXB3M
NoJ56FPHtv3x9+C56B5CLJ/+Ya8SLgfqVwwoK8FgoqDzEF3nbhf/WCUyph+gHdP3
D+jMk7t0tvIW8Ne4TGXenoxBznZxgh5ObpLlKBKPCGJkKxpfuq9koH33MmY/WoUN
7uh3F3HI2sGr7tY/xaN8H7a9A4mHzipj8nqaAsjAJppIpioecGCFVtkY5q0jfxLC
aAc1o4zoimdPs9q9mu/qhgKNxWkoTYnwvtWHuwqEOggvSb1ulS1SPS24VkKrc4LI
XMGbA4mQOuFwZyG4FVfvWzbnhsHzDh4cgHaVGra6z5zoX1MUrvieCWEji+Ul1VWa
lUJ2sTilvSGkwjGcMUSki5p9GcU8dPXwqKiZqDuGx6Ps4aQsw0vz286BnBeVsusG
qLRH4nkqbF9xCEz9h71mcU6WMu17EsG9zMoCg5K4EZ+RIG3cgWq0dMWW1LqtRn7S
2YqayY3+UEyMPN146R1V
=q3Ix
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
Driver updates for ARM SoCs.
* Reset subsystem, merged through arm-soc by tradition:
- Make bool drivers explicitly non-modular
- New support for i.MX7 and Arria10 reset controllers
* PATA driver for Palmchip BK371 (acked by Tejun)
* Power domain drivers for i.MX (GPC, GPCv2)
- Moved out of mach-imx for GPC
- Bunch of tweaks, fixes, etc
* PMC support for Tegra186
* SoC detection support for Renesas RZ/G1H and RZ/G1N
* Move Tegra flow controller driver from mach directory to drivers/soc
- (Power management / CPU power driver)
* Misc smaller tweaks for other platforms
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZEAZuAAoJEIwa5zzehBx3jCEP/1dcXY746rQoOMUDPyWF5+SZ
w0l8dHUQhu4WjNGryfb9DbyiE3d6xlvPVzr9AJeAg6c5I+iikgeogS0XHNpWCU96
FR1Ftb6zo8DIaGognBL9bK5HM7NXjd/EKBkMk0Ggs9/NRFUnakkbpdfivsl2BACx
mCGo15+kbgQSQsMJtd5/KfsgY5h7lXJG0fZ8LV5E1E5BSa/AofZtKVgCKfhbd0zV
gQqm7xfxtURHtucc7MYNEoKNk5rlrZhOlG6DdG0d6+rscCBrmL1I5giqm8y24+wW
z+JJuk21+oVtltLz09JuX51xur3CGyJ+qNJdRPE1P1Udn7wj5zA+ew9qqJi1cgNf
63tBxooBpH6R8dGcOfjKECD6lBBqBr/Dd8ReWbMyn0XF1HMAxgpfPtExu9WcDzGu
9Fr/shUiEA3jqhbzSy6DCHugpnHPdHPyY64MqzisgOEVsituQ7MSefTIGSNusDlk
K36I7j93mDAF5y2fTXqbjZKoRuu6KCySvGDXzBqGwhcNzUQk14iPwjtMDZ/l9Raj
sQJCUxHntUovHs+VTCwS7ahqZyn0VRNx2bt1aJXNHKzuUovpA9/X5X9HCRZJDovB
0bCGQZ124+H/VsWvSjVtIh7oknU3vSQJPxS6KLKoi3rvywuqW562lGjCTqvjBJKD
FMZ5NA8VoWXM2rgTDOyx
=B43K
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs:
Reset subsystem, merged through arm-soc by tradition:
- Make bool drivers explicitly non-modular
- New support for i.MX7 and Arria10 reset controllers
PATA driver for Palmchip BK371 (acked by Tejun)
Power domain drivers for i.MX (GPC, GPCv2)
- Moved out of mach-imx for GPC
- Bunch of tweaks, fixes, etc
PMC support for Tegra186
SoC detection support for Renesas RZ/G1H and RZ/G1N
Move Tegra flow controller driver from mach directory to drivers/soc
- (Power management / CPU power driver)
Misc smaller tweaks for other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
soc: pm-domain: Fix the mangled urls
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
...
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved over
from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using arm/
and arm64/ as include prefixes. This will avoid other local hacks such as
per-file links between the two arch trees (this broke for external mirroring
of DT contents). Now they can just provide their own appropriate dt-include
hierarcy per platform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZEAoxAAoJEIwa5zzehBx3li8P/iIMy0HmGuJ0JsTldMk4kgkM
1Ci/gcgKYn43m68RwvZCwkBxVibqCdMbBtLHCUt3ScGIYdj6mUG8axRHvFW/tsGf
BP0Y5pxm7l1BlHOKed97bJUeMyqqG13szzS7aB5L6cyZt41lAAkpCx4OFAuIlaxo
XM1v2xRSxqSf/zp4px83qX2hdHIpe4ZGlDiNh8rCBBnKMY4PqhK0V7TFLPOKbFnr
stIvD1TpvzacN67JVo1En0rCFgXSCwJ+CTumAOIx4tflV48ymY5THRNtI1ogFosc
1IfOxnC9DyRVM2ubFF7/ZLFbmn5KHu6ZwPLN+8Wl2McbT96PAtJ3h/zgTnuk4Tvf
GaAfqcyAXFeiZGU+bkkGiaQwXRDBroxVuNFTgERNgF70GUrDpBzd3tJO2rx7oZCS
Rj2QvKfBDBr9g5ldVGjOBIq/G9DeN5TtR6gyr/hCS/nm0NlYQ90Pzing0Nj8PDC9
/AOa4k4wUWo/oaFucBEeATCxto3TKpmBuP1I31sWG8StKVSJbIek2dSMcWSVFrG5
6/pzmuE4C7ZlshcFAUOeHxMVjBhTya5mDZQgZhCAnwhVMzrrpMTHTi27nbWcv/k8
9TH+ig5DoKL65FFE92ZkEb4S47SaD2+qKjEzJMDNQzc5WuY4l7pfDQoSn3YLjzKZ
xSKQEsmyOW0/0v8ecDKP
=v6w6
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved
over from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology
DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more
description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using
arm/ and arm64/ as include prefixes. This will avoid other local hacks
such as per-file links between the two arch trees (this broke for
external mirroring of DT contents). Now they can just provide their
own appropriate dt-include hierarcy per platform"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
ARM: dts: exynos: Use - instead of @ for DT OPP entries
arm: spear6xx: add DT description of the ADC on SPEAr600
arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
arm: spear6xx: switch spear600-evb to the new flash partition DT binding
arm: spear6xx: fix spaces in spear600-evb.dts
arm: spear6xx: use node labels in spear600-evb.dts
arm: spear6xx: add labels to various nodes in spear600.dtsi
ARM: dts: vexpress: fix few unit address format warnings
ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
ARM: dts: at91: sama5d3_xplained: fix ADC vref
ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
ARM: dts: armada-38x: label USB and SATA nodes
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
...
Core changes
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources.
I have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements
- A whole slew of drivers have their spinlocks chaned to raw spinlocks
as they provide irqchips, and thus we are progressing on realtime
compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZCusBAAoJEEEQszewGV1zengP/i3YgmSXJdaf26t/NxG3klU3
qx3akdQ3gEQ6BOlIY7Ew+b6qgMJynYNZa1trZgqTgLxPEKWjidyCgz+LHQ0OY+ir
a7x6wr+gBj5WlgV+nBjVs4l6W8pVKCfnap/04OPEQDpxZOHs2LU5pqxxUZ9AxkKS
urDFMDX55baFviQ+xAuHgamok87YoGP36A/e/fHIBepZmnochf0mCcPfIh0t8lRh
s2x29PN5ZFRkl403RzjZfVCEMr9bMnSqmDquvPO++Kq0bL+3rOhuMErocd1Bg8ao
LxBktkryujTaw699xK7Rq5SwcnOAPpaBY4NTmwsIJvAJuCh7qLy9JxQSBsSOT2bx
61NWUt5T/Xsi0ECYZM4YvsNpUP6XrpSTyG3c8T3fY9vXYLNKZBv1ht6OODpLeuke
DxULAWP+DdzUS8a3qfKQvIJzSTloU31a1MBG58DWNJ072EQfa2YNaVE75VQk/z5/
0xZbSHdPY/0Xgx8ltpKu37bSO676JiVQZZ1HEAuti4h21+USYueYD2L8/Bx4k9e/
4UaOcw3MaCDHP/sf5hg17kQBjhhS0lV9Zv6H9QbHZUocJTJlIU+vXtgkQlrfi3n8
8j5m+ywVarmLtPqg1j2rqcw7LBCPe0qRXH3e5X/YmNMc3rH9bQz4cTo8ZSN9r8zS
c17zGbbAqlGsBkpFAbQz
=DGPb
-----END PGP SIGNATURE-----
Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.12 kernel cycle.
Core changes:
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources. I
have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers:
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements:
- A whole slew of drivers have their spinlocks chaned to raw
spinlocks as they provide irqchips, and thus we are progressing on
realtime compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot"
* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: f7188x: Add a missing break
gpio: omap: return error if requested debounce time is not possible
gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
gpio: gpio-wcove: fix GPIO IRQ status mask
gpio: DT bindings, move tca9554 from pcf857x to pca953x
gpio: move tca9554 from pcf857x to pca953x
gpio: arizona: Correct check whether the pin is an input
gpio: Add XRA1403 DTS binding documentation
dt-bindings: add exar to vendor prefixes list
gpio: gpio-wcove: fix irq pending status bit width
gpio: dwapb: use dwapb_read instead of readl_relaxed
gpio: aspeed: Add open-source and open-drain support
gpio: aspeed: Add debounce support
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: mvebu: Add limited PWM support
gpio: Use unsigned int for interrupt numbers
gpio: f7188x: Add F71889A GPIO support.
gpio: core: Decouple open drain/source flag with active low/high
gpio: arizona: Correct handling for reading input GPIOs
...
Core changes:
- Add bi-directional and output-enable pin configurations to
the generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- A whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- Switch meson driver to get the GPIO ranges from the device
tree.
- Input schmitt trigger support on the Rockchip driver.
- Enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- Name the Qualcomm QDF2xxx GPIO lines.
- Support GMMR GPIO regions on the Intel Cherryview. This
fixes a serialization problem on these platforms.
- Pad retention support for the Samsung Exynos 5433.
- Handle suspend-to-ram in the AT91-pio4 driver.
- Pin configuration support in the Aspeed driver.
Cleanups:
- The final name of Rockchip RK1108 was RV1108 so rename the
driver and variables to stay consistent.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZCG0aAAoJEEEQszewGV1zBpcP/37y0m2ZFIqVJrqlPKVeZbRa
aYwsbY3l9OGeocLXSRWaqLJkwJ+WaG8ascoXHLMgk4jFC2CutwUea0fzhy9Li2VO
Sqd/BN9iNd/g2lTf8o37NM5qYF5IvStZu12DzFPRFpec6pEiYOHVmRiSlIK5lREG
v/NGNAIzLPH59jRHA17sLT1lkHmiT43S4Gm38nvpar8vfO+2UkAwGVPQPC8dGuL9
gydMLLtx3d1SzWqicbMSICa/F7kjWz5I4jL6KM7ohVGXgDn8tdZk+7rERfBD9qoR
eDNPZvXajaC6y3S3h6Ynv094X30w3VA0xtj9kPVhJsS1yUlVli5GlC3WHPArwrRQ
sXx29UsdTmAjzHHns4OZfxKnEVvHbXtW1XmX+ks248f/k8hCVWpQA9ZENvVHjLvu
NkDwXOmTWOxjutDveZqm7RM6z+99+lRgzLgwB3GMENIUC8ohH79W/R9GYHvrqOZI
hWX+G/q3nnnW3cIPc15rN2MC3fkjE2mdFC0N+/kDlKtzPabCS8U6JZsfQDulX5m1
I2xF2DY+1WWCy1mMDpyTdYNDlkOGU8j/N5MXx9z1629m+vjg0KZo35+mGwJh5mA1
gQ6rI3DdhS5qVK2Gj/joYkwQ1cKpdEtljlpI9A+WdXx1eO7RKVK1m1fxbd8c47L/
I0qdXsL66ZtiKDOIDPau
=BCaA
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.
The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.
I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.
Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.
Summary:
Core changes:
- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- switch meson driver to get the GPIO ranges from the device tree.
- input schmitt trigger support on the Rockchip driver.
- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- name the Qualcomm QDF2xxx GPIO lines.
- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.
- pad retention support for the Samsung Exynos 5433.
- handle suspend-to-ram in the AT91-pio4 driver.
- pin configuration support in the Aspeed driver.
Cleanups:
- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"
* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...
Add missing pinctrl binding these which would be used in
devicetree related files.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the missing reset bits of the ethsys core to the mt2701-reset include
file, so that we can reference them from within a devicetree file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5feFAAoJEBx+YmzsjxAgzicP/2zx3xYRy5C69wI5IRxAMDjg
3AGgZgVXH/ir9CHVW7oGhBo9VdgbMdTZAJCA6WKBVjpjSsRkEVeEeRMTKAPbBBll
u5bFpQ2hX4WnGFlILAfXLtJJ39pEPZnHUN+ew3umR7xXMm76o7vB8Z59fd9qkgpP
wXwwZPDywtLusawxDjci0Wrzek8MHkFA6WwXnlnp82CbG+tLOe+o/x9kv125x9fT
td2POgaoG2FEBL1GyfqY0uzmNKs8oHwgbWmepsu5xFmmLYS4cwVHHIMAm3iOEmF+
tPZfeYxYVDY3cDfPhyj7/in3ej5SM63ZG6YSZjd2z/rXhGrcCNCmhFEwk9ie81oT
uHQ6B7K4hAtV1zJ7wZZJD/vqZewOaTcb/V9S7D1bGsBLcBrswOp7yaf2ECnhSQu0
C20Vp9xFdmSTReGIpD6+HCVLYSU0DHOVx0D/+dPOTtrfJR98xiEvUPekuo9yRmuc
MIBFzRJ83x9Ee5PS2jBju2V7VaGD08Q6R3JLDkCgUTaBTZq/jlNGc/9DD6llFM/E
idQ6j9dJnSzU6C4QVClIxBQHJu4kGNUUeWAXqxBTEh7jUg5bnKjUXox0W44RzqPP
j/ZWB60xLD/FdbaGQdxU72uFpok9Uc2fySvQqAwePe5F2j27IIMOKu/CpFmefc17
Ww+4lw2nbR3dypCxt6C7
=V49g
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
* Add support for R-Car H3 ES2.0
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY59ObAAoJENfPZGlqN0++mmAP/iLPRVjE0DoqVVQbNeIq4pOI
0HaIU2MZH6cPN2868CBp+8/UsPQXUBtpBRdRsc7+B2gSQteFhEZ8b+tTJ007BohM
YO4XSSfwEUedKoPB5N88hleGrXjvUbNBECOeD5XSOX3X9qQLDUkzpgDgfL0WPl6D
gU3G7IitR2KnBTz5n8XbrdTVccZbafXutj3Sp8pTxd4Yc8ajL8MkxbwTjlGratfw
sOUW1zxIv7c9eanfbYZQ3ZGNm++2w/WnqhPBTYfxcBVK95dslWjkxf7HawujeaP7
CihAakoH9QoYsrnyEMbMn4xpCJEYB8U5zaIzyOFHhGCtF5AXUrKFcn1DMpU7sORJ
mu4UDUHIugGsu/RdOcOdB/dZ5GcfFtVehDLKtAGdoAwyc6eY9URAwOlOV9abOCtf
qWSGHv0dKCVg5fLcuCzXMYd7DxXN1X4A0wj94S6XF5S1/wcWJaOU2uJKPSguoUzW
vQt4jIM7TUUK6YAVj0xec40lXf0AuJ4FcXI/9TEnYnmqzOEwZzKzrlMv3xnqp08k
jQarhWJLvN23lDAtGOorLJKOZyveXy0E3I9IJT8PgZpGmOlijSRBzhXsN1NeGsYo
663+3feI4Qe5vtu8Obv/vA0BcYHiA+AcEBwWYFAZOGGSM2IucORxX9UAu8XBmtRB
FnS/AB2yrsoL9VjKgeYt
=m+ef
-----END PGP SIGNATURE-----
Merge tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Sysc Updates for v4.12
* Add support for R-Car H3 ES2.0
* tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
base: soc: Allow early registration of a single SoC device
base: soc: Let soc_device_match() return no match when called too early
Signed-off-by: Olof Johansson <olof@lixom.net>
Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board
Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY57Z+AAoJENfPZGlqN0++410QALS78C/4O3vVj3AXABGTnQBc
B0cIlfmw1plyx1g0GhZJZYfZ/8bDjdw4yhu7xz0pttWSyfNZpYS7TMf2Uyf6bWtx
lMP3N7HYX12y4d/TKmg/w8zNT/P5sBSuAcDwlbRMAKVJer0ztECHmPLawJesF6Vw
2n0VZZpi1A9n4riJukigbiFkRPNjmQAIDB3Rx1afXeyVtUVwImvBb3vJoZHaYJ+T
MWaUQ4N+ve22HNm6k8UxJqglDxf9GO5k+SXppPwqUsZlHF41nuR5zWOWxUQl5SCQ
G2OQGLcR0iXPcuiFbb3DScuVtwXlm8AgZNOEOGssukC7JkwTFvwHJWMXFBt4ZlPS
yDFxTcCqyUtI4NbcsLO3eIEddzG+07V5UwWQw82LXktY2/rYn0I2jgcoAPh6zVou
gkA68FaMZSp2WYMfd9EdppyrxaLGbSSi/g3BQnV3HJgYjGqwtb7QSRVM2tmeMEnp
RTrAnmTYfRPm04FYyBlwmw7YaDiia5MHp4f45B2mWcXBDlYqepvxDHCyj1lX2ySL
/QmVPGrQGSWEgbLhB1kKzSpI90zZBJMzNWE7GaYhb5dXZW2SpjkcpzhHxLtB2BLR
xIHIlQ+RHiS0fOPFll3/wfvGDoN1H+P6nh1kz0BJFeQ7ph9iNNVnD9QOaXqePKqL
rlbJMygQXSAQ6A8lNrS0
=N8Dk
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.12
Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board
Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs
* tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
ARM: dts: genmai: Enable rtc and rtc_x1 clock
ARM: dts: rskrza1: add rtc DT support
ARM: dts: rskrza1: set rtc_x1 clock value
ARM: dts: r7s72100: add rtc to device tree
ARM: dts: r7s72100: add RTC_X clock inputs to device tree
ARM: dts: r7s72100: add rtc clock to device tree
ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
ARM: dts: r8a7794: Add Z2 clock
ARM: dts: r8a7792: Correct Z clock
ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
ARM: dts: r7s72100: fix ethernet clock parent
ARM: dts: silk: Correct clock of DU1
ARM: dts: alt: Correct clock of DU1
ARM: dts: r8a7794: Correct clock of DU1
ARM: dts: r8a7794: Add DU1 clock to device tree
ARM: dts: r7s72100: add power-domains to sdhi
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY6zd4AAoJEFBXWFqHsHzODtoH/jwTFRhAhfKG2wfplkP+U4HT
gijXHDybebRGll2voGAL7YX7GPhLcy0NSGdiK/ckTtHlvR4E2uxcwaIwzXIE1CTb
MXfv7p+3FXhjcqgbvl122hnLAMWOYjcbH3tFzBy1jlpGp9oEmHx4OtpdlgyD5GJ7
+En6aDtbU0g8aJg9ldZfO8iSAJz1CAqpap+FRjpcPX4xXflOQwQfxJNWuDeg75k6
U3zB2r+lbmjIfohUHWAnHsU2Jf4WPrBrjVsj/1YsiE5rMNPfxAEPYSQJAumG7JtO
qTPWf3qJnSyrWBscPRR3Fs//11IgXZXSCWBPBZjng0ELFS3Rkdvp87etjZraSjU=
=Sypm
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers updates for 4.12:
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
* tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
soc: imx: gpc: remove unnecessary readable_reg callback
dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
soc: imx: gpc: fix comment when power up domain
soc: imx: gpc: fix imx6sl gpc power domain regression
soc: imx: gpc: fix domain_index sanity check issue
soc: imx: gpc: fix the wrong using of regmap cache
soc: imx: gpc: fix gpc clk get error handling
soc: imx: move PGC handling to a new GPC driver
dt-bindings: add multidomain support to i.MX GPC DT binding
Signed-off-by: Olof Johansson <olof@lixom.net>
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY66cBAAoJEAvIV27ZiWZcSAAP/3qvcWDNVwc7Rg5JIcbvBP09
mBbcutrHmFVi5Swd3yuTyNErRFliVsdDV3dwanxlXOojqYgE4WpJQFKtXr8obQUa
q3yk+gzMIS3+P18dJPU+SFsCwLDaUF4PkiRm3vd4Oc6fgPfqCbWfYcS6jOhbBdzD
GWAMp6j/vn3Br3RSFe2NgH43kv2H4efEh0lrKj3wk2mCDF3s69PaMGPLgCfeV1F0
pYwyO/2v4TWuJkO8U7g1XyvK6LRO49mWDKdqhP0hZpr3DJP7T5u9E4bxScBwG2GY
ENURvZpl3Kd1thfR9+7FkwNg0Z7Y9hVNI5763JzLusd6pw1y2jDU9oEESpuVi1FH
9dwqloiLuonYSPvAM9XS84CXnguFoqjndf7Z3d9yliS86GRn4g5B5t20rlLtSE+4
o+IcLQy6z6CpDHugTzav3oBsscckEiWsmX0X6Jym23+buzFcHWOPOQldIUUSDDoq
9oct1AxBrQA9F9KspaiWRy38Bwi8qRT5FT+BfBai3y45FeEKdRFUghIwdeqm4F2v
1JulIiPelHUtELAcAEJFRVQzgfSVuGuXCAHVHpgXE018UnNvhfl3/VtUtvLI71wf
jukY2JIJsG9r/NHR1uZU8LGN70bNUjHXwuF0R/zh2zwZT+mDgxEe5zOlCbQyYJbt
uqVy7+asSKcbOLabW/Ae
=5zO6
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
arm64: dts: hi6220: Reset the mmc hosts
Signed-off-by: Olof Johansson <olof@lixom.net>
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY5n1GAAoJEHJsHOdBp5c/HskP/RK+Q939tIdFI2joV0R2uBF8
sSPHHfduY/GZpy+Mlqxjo5gYE1AxGY+rOw0YNWWvZ1hpkIgP4g0zC0yCxQaLnYF2
VuEoZwaEcGDKsmTISoKkMp8tonxW2EOQUsYty8Iq66rGsrRgTVqmsM8ApJSqyo6l
+nD/AQnWboNnKiJ3t6HE1xc8YLWFPiLfl5EgzR3OyXKfrRjQ7mg9SEddmnrOunLd
T8fqVgAtOgcb7a5LIuGq/4ddSQPm38fDYSc4QtSmhZfgke94+xKHrBAcBVXNJOaC
ESxvhu4l4xarj6aagWz7TmokFt7JNXgmcC9nZkU/YcKdidVN6dhF+MraFQpZnMAJ
ZYFfz++6gNiFWKRnaQWmsXaCzgxlnpajJL5th39/izwFHKMWU87lXO5WSZnOdosA
1Ph8M7zAmxjAE0R3TIFjRnT25spYxYqWNFhrCSpIuYODZNefAZqaJSP6WG7ab+Hy
u9qpVjAYCxir36sS/pTHiiGDLlGiUM+3lOtT9o5xWZCv9gBLiYLziW33nKbgQR2s
4KrfKnNq4Kkvx3rHM30GPzVXziliqS1TF/j6vl8Tx/m/RnXtT2DBknvW5c43NBbF
Ad1Ux6JJ9M3b009wjo5sEWzemFlKKIuWh0ekvr3YYcVlGGqXDK7os4fvfsFPbHv+
6CmNAQt6rbbGI+8pJC5w
=ayBe
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
ARM SOC PM domain support for 4.12
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
* tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
Signed-off-by: Olof Johansson <olof@lixom.net>
Highlights:
----------
- ADD RTC support on STM32F746 MCU
- Enable RTC on STM32F746 Eval board
- Enable clocks on STM32F746 MCU
- Enable DMA, pwm1 and pwm3 on STM32F429I Eval
- Add support of STM32H743 MCU and his Eval board
- Enable USB HS and FS on STM32F469 Disco board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY4n6WAAoJEH+ayWryHnCFaXYQAKmOBcBrU2RiZt/tn02lhEJI
/BKTjFUBg9CCSMqT8xJvDtCJ3YLUwxqo4HhkvKnTZh7AQ1mSTdVScKrB0Le83271
IOoAFBmCZCn9ShSgclBPiold1q5i7g/hZRagQwNwXHdQXt8GZxhpVzaYgZj7EtQ4
B5ikmQCT9KagPSiY4M6X1pzRPRmqcN6alAYsIO8SoHrFpBXm8/TWqspn5pPhojIM
4oWbGEwAxLR4J86TA2Eu+Yp/8FvGX8+W59tFbarlBPloKueHADZ72MfrTZ72vXf6
y4s4JGctDOiLqRFBR6Pp3i8/F4d2pxtd7GsWHR12Mw8lQGHHkKZWs20vri+s6HiT
qkjKWXdV4mwYis4vUB997NOYClbqTbURcUt7uRvFrDXD2gg3TnRGkP5WynEX8njS
cnRhJ+1rS3iC2rvNtRGE9aadRRtxXVqVQ1HA2EeBeNGpVgFFPbdhPpt2ZDhC2PLf
FRYQnxxVAngionqxNGytwKTHXSsVYufMINPyUZWxqUXN083+HAWemJCUTd6cC1ia
I781iAjQDWyQzrG8jQtsEXPT2rSdrouVzu0CG642EDuU81CkAWz8vBkrjPj9m+9g
fcd8RhRQTvcz0rePNBq/OLRojA7bVsDBBikAJJh6tCnwil8oJlaJ5DSbORe8J8Ez
DlOoNIKk1byGfN6LrxKz
=l7eq
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt
STM32 DT updates for v4.12, round 1
Highlights:
----------
- ADD RTC support on STM32F746 MCU
- Enable RTC on STM32F746 Eval board
- Enable clocks on STM32F746 MCU
- Enable DMA, pwm1 and pwm3 on STM32F429I Eval
- Add support of STM32H743 MCU and his Eval board
- Enable USB HS and FS on STM32F469 Disco board
* tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
dt-bindings: Document the STM32 USB OTG DWC2 core binding
ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco
ARM: dts: stm32: Enable USB FS on stm32f469-disco
ARM: dts: stm32: Add USB FS support for STM32F429 MCU
ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board
ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval
ARM: dts: stm32: Enable dma by default on stm32f4 adc
ARM: dts: stm32: enable RTC on stm32746g-eval
ARM: dts: stm32: Add RTC support for STM32F746 MCU
ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746
dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
ARM: dts: stm32: Enable clocks for STM32F746 MCU
Signed-off-by: Olof Johansson <olof@lixom.net>
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJY5CeGAAoJEFk3GJrT+8Zlp8MP/01Po8BB0Hamo3SGIckzHIXn
4yYHnX4kYIGAHw4E1jki0Kz/3TxUSpUm4LWkcYloesPxnXipy2rlYJDhoFF1+QBM
A/Y6Tx9G6sTEmk/20HDzof7N1DzfGAdj+NJd3IMXaOIbP8XFBXgdRktB2kSUu0ZM
YPvlh5EjkWVhE5I+JqIfxSqAHW9+DOf17rhmch1wEXXMuVbtqPhm/DFd9+Ux+4WF
VoQ/dP0QLv0tszruJeI/bEqjgMGe+0feZt49aOpGuFfqVUP4tBs0fwOdjg6ELCrZ
Spw5GAewa7delQP8ihnC7n4wiV77k/qulReh4jExCt8s8L8nbkOL1naQlClMJfEb
RkoHC4MH0xxc9Q+J2l00DkHR7DgM2BTEUcmPvXkr+WBGJ+fN9gb3iIfJx9uY3DsD
W4iCkY+oAB7y4/lfa1LoImbGrrm9PmpXZR24TAkynaL2EOiQ7BtDuZsIFqu53VTn
O6UCIiKYlCtXrTzbpP/z6kbQ/8oASVE1hk1rfYSNpLU05KgCBFfS6pZWQDC8hJJv
UhK1nfxBrzIxQ130g9oJqFU5uwqheZJ4DLLBo751JLPfAPBI5tftxkHUOYWFA1+s
uoHZSDnKNiwnS+krjo2kFREF3etY/Fqp98OP2GYuP5H+MPsL1mIFxX/y/MBsDGwo
rH2TqHIyoKSPX5sIvS8I
=Tz8Z
-----END PGP SIGNATURE-----
Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next
Same great taste as the previous pull request, but now with 50% less DT
bikeshedding!
Amlogic clock driver updates for v4.12
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY7X0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgRKaCACXoa3hjtS3CSqyJZQyMPPQ0Oda7bblrubR
CE4GmuoZTnX/mUENFEmY7R+k0Np7b6ijPgdiFNpeZo0bpXAdi6bNjerG/QdRPV/P
yP9usSk/8Tx/kY7vnSNTve5QiIJDUoWKGY8fn7ped+GmM7Qeb3/QbWR4N/fL4vVD
nSZnKDO7yGMxLqWL0/QzZyiLzXl1ViEkPWFTedMf3cm0A48p8M/K5jinfMvl9I+o
6e2TIsc2zn6vRKuoGhjqcaRxhtRRV9c2O8wVAcA6BLo/kk3pA9ZTU3QJPsqEcN6A
BTbANYfXiQF6i+Xp1YJHcE2lNQ/sWZOTQtLqY9SL5WzMETMTETT5
=In5R
-----END PGP SIGNATURE-----
Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY3h3eAAoJEEgEtLw/Ve77F5MP/REcR7bb9TmdCDwXFpMXmZtw
jigpASslArlBsBfWsGX3oalkrrKLY+qs8d8++9+OIYdvf6stFNEH5E0PoOTOmNGY
bs6NnXNXxKoRIe/HK2bXYav2MAmf2fDNWFSnWapygV9j8CjudCEPrK+GZcWI+0ED
Sy5zE/exnPb/oZp5VutzZNiCAuI79iXjtIDOZDidQxwzC/AOQ2wq99ieclEafABX
F5XQkUtYjEzu7DgX2Luy0f7GMlNCVlaYbM1oi41Reka9UF8Ei3G7tLX+/qNgkyu3
U6HMRbiQBkOKVBAfKetmOyAJxhHk1R+Q6e9Qm3LJqHVt9Ar9nclybEcRMcYMJFpB
aF9mehg0U/3yyX3IW7arXTCLegSPsOLn+Hgo1b8tG2BZKsMQrd86elVVGPODkDZj
CQyge358wvMKzqTozGjP9s8TetU0lpQI7HrK0/X0dNmYnJlejJ0mi3cSUu+Rp8al
+tbMJL47W3JxBFhh1kBJGMoUW3glbDYdlwyvGy/Fsl84TCWD6bmKh8AhRQrYbOR8
Jo3CiH22HPHAT0TWXwOhEuB6TxDacpA7Wf0dDN0EPRZ2kGrRvjvxv7zg8BPKCGcA
G6uTX+Wlov8TTwYzluLtfbbRS0Kmcx0ZcuKAmgoV9991e4IC6YKaBok4ArqfEdwR
BcnSkpRriiVRqbj17Hdi
=rttL
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
- Add IMR clocks for R-Car H3 and M3-W,
- Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add support for fixing up clock tables
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
clk: renesas: r8a7796: Reformat core clock table
clk: renesas: r8a7795: Reformat core clock table
clk: renesas: r8a7796: Correct name of watchdog clock
clk: renesas: r8a7795: Correct name of watchdog clock
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
clk: renesas: r8a7796: Add IMR clocks
clk: renesas: r8a7795: Add IMR clocks
The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Extend drive strength levels of the pins for Hi3660 Soc.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Power area A2VC0 was removed in revision ES2.0, cfr. R-Car Gen3 Hardware
User's Manual rev. 0.53E.
Hence remove it from the power area table when not running on ES1.x.
This is in line with the goal to:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH/LOW is used in the interface for setting the pin
state to HIGH or LOW when enabling/disabling the interface.
In Open Drain interface, pin is set to HIGH by putting pin in
high impedance and LOW by driving to the LOW.
In Open Source interface, pin is set to HIGH by driving pin to
HIGH and set to LOW by putting pin in high impedance.
With above, the Open Drain/Source is unrelated to the active LOW/HIGH
in interface. There is interface where the enable/disable of interface
is ether active LOW or HIGH but it is Open Drain type.
Hence decouple the Open Drain with Single Ended + Active LOW and
Open Source with Single Ended + Active HIGH.
Adding different flag for the Open Drain/Open Source which is valid
only when Single ended flag is enabled.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a generic power domain implementation, TI SCI PM Domains, that
will hook into the genpd framework and allow the TI SCI protocol to
control device power states.
Also, provide macros representing each device index as understood
by TI SCI to be used in the device node power-domain references.
These are identifiers for the K2G devices managed by the PMMC.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp
and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the missing module clock for the second channel of the display unit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch lists STM32F7's RCC numeric constants.
It will be used by clock and reset drivers, and DT bindings.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[include rename in rk1108.dtsi to prevent compile errors]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYz5TPAAoJENfPZGlqN0++JQYQAJ9qo4FOHP2XNttgK6b1jSg4
zSsjRats9bHX6Rs1dhT5KP7BatpH8kgLoJEqQThXWEq3qDNvDrWMd99yoOF8q1A5
tnpcFpzFZDf58J1PR0bPyWSZC6prLyV63Zinx6ZyTVDGm83gXk7TjfPRk7MqkPbr
DP0spMO/5UXKPD6gE9hShz2WWCh6ZWvj6yUg+7ddjIYYYJwg+3MnNL+IE2H5BBaD
VLlrxW5VrFdN1oxL+SpkB8DfcgTawJSTMw2pHzSqLT88s9ADAwW3IZeklpySztuk
CEuxpi+0AouXzMfL4kJB4HTCXxOTGSpQVYEzUEWCID92eXyoBj08qghU21WKk87p
9OJZRd3xeZczN3ssfSVTLUp0rUrnS2Zyc3QOFRrA7gNLiykmNgurWrXT8e3yE9wa
Z0Htb7WhUBlq77TTjDb46FMKCSdVcb2CbK2qtbyqdtRmsDB0+51DKG3bOsWTMWJW
EMgWj4PsYcjBr+27q/8DbQXigX4c6jb3p/s6ouelEiN5ov78pwiNtBMBjiMxo1GI
Pb4aWlKBDOxx4/JeBIn3pWKozbFIajPK6RYlHzd0g3SKFvjcEPlzqslsJTlye5ay
CKHantmnzlIf+iJSdkthtD9ETIWhp0BvgmJ+BgwuffRpeaGjsXggkQjxGQBgRY3/
s7OWxr+5HMd+1Egj3Tg7
=2cA1
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.12
Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC
* tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
ARM: dts: silk: Drop superfluous status update for frequency override
ARM: dts: alt: Drop superfluous status update for frequency override
ARM: dts: gose: Drop superfluous status update for frequency override
ARM: dts: porter: Drop superfluous status update for frequency override
ARM: dts: koelsch: Drop superfluous status updates for frequency overrides
ARM: dts: lager: Drop superfluous status update for frequency override
ARM: dts: marzen: Drop superfluous status update for frequency override
ARM: dts: bockw: Drop superfluous status update for frequency override
ARM: dts: porter: Always use status "okay" to enable devices
ARM: dts: r8a7793: Add INTC-SYS clock to device tree
ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Add INTC-SYS clock to device tree
ARM: dts: r8a7792: Add INTC-SYS clock to device tree
ARM: dts: r8a7791: Add INTC-SYS clock to device tree
ARM: dts: r8a7790: Add INTC-SYS clock to device tree
ARM: dts: r8a73a4: Add INTC-SYS clock to device tree
ARM: dts: r7s72100: Add watchdog timer
ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC
ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- make reset drivers with bool Kconfig options explicitly non-modular
- fix uniphier non-static symbol warnings
- fix socfpga nr_resets property
- new drivers for the Arria10 and i.MX7 system reset controllers
- fix sunxi 64-bit compilation
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAljJUToXHHAuemFiZWxA
cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOvFnxAA8ImyPCzDDMtgGo9zMRId4ICH
/YbbYrc5Gp3vDJJnJYVD0KCOT4174yinvHxrxpmjiftcZWcQRNH881uFJpgmXUjW
zT7SapC0REWMx/DQzcR/Gh0smiehU1hVi+PSosNNqwbpZZrlxOAgGSoFYw87pBtJ
gSOwTfUWlSEVMBtsQpTeO7cUzc5HvxuIvu/SMORi3xP1nukv8WIDuSGGFAWv235D
OQOe101hQBO64yyW1J2X6+UMH+fHgmVT9qhqT6uJgYfR57pO17vX1aF/GEP9GV9R
/vja0Y8hMNyvbc9CcJJQjR6BfXIOjrCYdDs+9nV4znYAcQpLJN5wfB6kDzogpH4S
3vgIsqT0OHYCdcXahuPuzDtE9zJ3oktyZT3MPyOsIkCwxGt5IJKRF9XGEGF3E/Sl
0yRpC45riac+8vuNJHnOe2qjRmx+zkAioyTPmYwPihwb1rLTYUtnqjat3egG1z0q
UZvCpOcuQ9X/cAo+IIZW6IhDf6cqWEPks3pGinJ5XZ66qoeW5UMJz8v+i7c2F0oK
LFLedERgaergvpAShiSeZTlXFkWQAJvGzDoCbpYTeQHELPV/ZJn88rJGP2DJ4/l1
7Sy5lyjFWtZqvfsBnoMniYc1XG2v5kztzAp9pZFEzBMHEVgCyJla5PxF7rDb+U/k
tzeSfwd3DUkT8qtB1K4=
=5xmN
-----END PGP SIGNATURE-----
Merge tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux into next/drivers
Reset controller changes for v4.12
- make reset drivers with bool Kconfig options explicitly non-modular
- fix uniphier non-static symbol warnings
- fix socfpga nr_resets property
- new drivers for the Arria10 and i.MX7 system reset controllers
- fix sunxi 64-bit compilation
* tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux:
reset: sunxi: fix for 64-bit compilation
reset: Add Altera Arria10 SR Reset Controller
dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
reset: Add i.MX7 SRC reset driver
reset-socfpga: Fix nr_resets property
reset: uniphier: fix non static symbol warnings
reset: pistachio: make it explicitly non-modular
reset: ath79: make it explicitly non-modular
reset: oxnas: make it explicitly non-modular
reset: meson: make it explicitly non-modular
Signed-off-by: Olof Johansson <olof@lixom.net>
Tegra210 has 2 special resets which don't follow the normal pattern:
DVCO and ADSP. Add them in this patch.
Changelog:
v2: add DT bindings file
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock clocks the ADSP Cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock
of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we
add a 3 new clocks similar to the audio* clocks which handle the same
function for the I2S and SPDIF clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Expose clock CLKID_RNG0 which is needed for the HW random number generator.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The Arria10 System Resource Chip reset controller handles the
Arria10 peripheral PHYs. This patch adds the offsets for
these PHYs.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The timer-ids are wrong compared to the manual, probably due a simple
copy-paste mistake from the otherwise very similar rk3288. And there
are even more timers in the system than the ones wrongly listed here.
Timer-Ids were unused both in clock-driver as well as devicetree
till now, so fixing them won't break anything.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock and the C4 power domain,
so it can be power managed using that clock in the future.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix typos and add the following to the scripts/spelling.txt:
overide||override
While we are here, fix the doubled "address" in the touched line
Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt.
Also, fix the comment block style in the touched hunks in
drivers/media/dvb-frontends/drx39xyj/drx_driver.h.
Link: http://lkml.kernel.org/r/1481573103-11329-21-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.
Add its support in our existing H3 CCU driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
These updates have been kept in a separate branch mostly because
they rely on updates to the respective clk drivers to keep the
shared header files in sync.
This includes two branches for arm64 dt updates, both following up
on earlier changes for the same platforms that are already merged:
Samsung:
- add USB3 support in Exynos7
- minor PM related updates
Amlogic:
- new machines: WeTek Set-top-boxes
- various devices added to DT
There are also a couple of bugfixes that trickled in since the
start of the merge window:
- The moxart_defconfig was not building the intended platform
- CPU-hotplug was broken on ux500
- Coresight was broken on Juno (never worked)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAWLmRS2CrR//JCVInAQKrkQ//bd8TCGXA0tRwDMEGejtWChZcNkGZDaer
sNMyE/c1p5+/4euSmf3jW1JsIx4JDtjr0psKeRpgYId8GVdvaYceFbSMJl6o9hDc
pm3sqb66xEgrWQoSBA2Urz/RhSIrxkYbuTpYbN4teV9I/IFgTUggaBSzfkq3SLRE
bEVSbCw0S/6t3vJgW4CKCI75+a3NexqImvi8txNwueQQMnDLnOkG97vMUQJgDq0j
E+CeOk0mvlGF+TiVoAhUxT3YIt8azUTfUVw7CBIRvo/49sUCiETk6xie93FaC7GI
Tmg9KK+oZhrmqt8PBGkikxQMHATnKrfJbMNi/K6nrxW91ylSkwTN/7jfhSjFDrdI
4WNB2x3u6KUnQ0XOKVY36gUnV8kJ/2K9pTZpq0K7m4czo8YAid9LumvDnqhPI0Xg
fXxq3YBx7AfzsdBL3+nQ7AH3tr9Bvt01kMZwYwNgpqtglEBScAgzyrPG/yyTBFq7
KOkoyNojTaHZHcDtYqSaxYls+2tdeyvYuQJ7QGQ5DJCW99NgbRuFfIUJvgwRPoKt
13ioIJxDUHmemR6xFURWVH1dPkkqwtJht7us5jcxuxBL9ZhmEb6vophvyxj62zTZ
8A+PE3cC1azhKph7rVrUl9KEoYZzedwDaTGBNpYz1gN7DxDvWHYINEPB4bBLzYmv
uWsSYVbV2Qs=
=A3U6
-----END PGP SIGNATURE-----
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late DT updates from Arnd Bergmann:
"These updates have been kept in a separate branch mostly because they
rely on updates to the respective clk drivers to keep the shared
header files in sync.
This includes two branches for arm64 dt updates, both following up on
earlier changes for the same platforms that are already merged:
Samsung:
- add USB3 support in Exynos7
- minor PM related updates
Amlogic:
- new machines: WeTek Set-top-boxes
- various devices added to DT
There are also a couple of bugfixes that trickled in since the start
of the merge window:
- The moxart_defconfig was not building the intended platform
- CPU-hotplug was broken on ux500
- Coresight was broken on Juno (never worked)"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
ARM: deconfig: fix the moxart defconfig
ARM: ux500: resume the second core properly
arm64: dts: juno: update definition for programmable replicator
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
ARM64: dts: meson-gxbb-p200: add ADC laddered keys
ARM64: dts: meson: meson-gx: add the SAR ADC
ARM64: dts: meson-gxl: add the pwm_ao_b pin
ARM64: dts: meson-gx: add the missing pwm_AO_ab node
clk: gxbb: fix CLKID_ETH defined twice
ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
clk: gxbb: add the SAR ADC clocks and expose them
dt-bindings: amlogic: Add WeTek boards
ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
dt-bindings: vendor-prefix: Add wetek vendor prefix
ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
...
to existing clk drivers. The bulk of the work is on Allwinner and
Rockchip SoCs, but there's also an Intel Atom driver in here too.
New Drivers:
- Tegra BPMP firmware
- Hisilicon hi3660 SoCs
- Rockchip rk3328 SoCs
- Intel Atom PMC
- STM32F746
- IDT VersaClock 5P49V5923 and 5P49V5933
- Marvell mv98dx3236 SoCs
- Allwinner V3s SoCs
Removed Drivers:
- Samsung Exynos4415 SoCs
Updates:
- Migrate ABx500 to OF
- Qualcomm IPQ4019 CPU clks and general PLL support
- Qualcomm MSM8974 RPM
- Rockchip non-critical fixes and clk id additions
- Samsung Exynos4412 CPUs
- Socionext UniPhier NAND and eMMC support
- ZTE zx296718 i2s and other audio clks
- Renesas CAN and MSIOF clks for R-Car M3-W
- Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
- TI CDCE913, CDCE937, and CDCE949 clk generators
- Marvell Armada ap806 CPU frequencies
- STM32F4* I2S/SAI support
- Broadcom BCM2835 DSI support
- Allwinner sun5i and A80 conversion to new style clk bindings
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJYsLxxAAoJEK0CiJfG5JUl0p0P/AiBaYvrmHBx3H9jdC3iQxd2
7luFN3OqpykmZc3xx2xO3WaZ96kwwxiMu8sj3+VQo6oCkEuOY2ru6uPiDOcF4P3+
8ku2taoWlESDbVLebVTNJoRXBaBLaV+9BCN7AKvXpVw+/UkJI5hgr0yMdh4tgtvu
K08tTMkDNDbA33KXuJo8/chQFqi2W6XBXk22YMkqqA8jx0F4EM759LcgUlD1YfBS
HKkgSOgsW3Zwhl27ZEAJMthcmS4+wFaEgFBeipg/hxTLI3aQtmDtRfXwg0wkbBx2
8sVz9SyBwkjOT9+41kve+Je94NK3blnJEjbxPASveMwyhdX1TlDQCPfrXya/1zxz
N1By1NpA6iEYwi4hy+OtBYlcsBHztAM/+eljDY2kEDvfiKjMa44GYmgBu4n8pq+n
75NJxws6ZkzPs5/QsLT3hvTaL1SNX6PaEW8HabDXO40ccZc4CYvFZVOXMAnKaXzZ
31hj8EvQ5x6hci+SPYyVu6j3ipOxN96VcZqEJ+hWyyuZEMK6Up1o/0lGZFgwa0UD
SIl7RiTFKO6ko+8hYlk1g0DGtEyWDsdso1Bw4zaHwMngM/CwjJVzpK5T2t1fJyEh
lN5MdhcOi0nsiRWdRxOwOlHDLf93qSo87mvseU1MCEXYN1aqTV3VxSm1YU8ZgQVk
sAjpsJqj45enfDa9BmIt
=o8o/
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The usual collection of new drivers, non-critical fixes, and updates
to existing clk drivers. The bulk of the work is on Allwinner and
Rockchip SoCs, but there's also an Intel Atom driver in here too.
New Drivers:
- Tegra BPMP firmware
- Hisilicon hi3660 SoCs
- Rockchip rk3328 SoCs
- Intel Atom PMC
- STM32F746
- IDT VersaClock 5P49V5923 and 5P49V5933
- Marvell mv98dx3236 SoCs
- Allwinner V3s SoCs
Removed Drivers:
- Samsung Exynos4415 SoCs
Updates:
- Migrate ABx500 to OF
- Qualcomm IPQ4019 CPU clks and general PLL support
- Qualcomm MSM8974 RPM
- Rockchip non-critical fixes and clk id additions
- Samsung Exynos4412 CPUs
- Socionext UniPhier NAND and eMMC support
- ZTE zx296718 i2s and other audio clks
- Renesas CAN and MSIOF clks for R-Car M3-W
- Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
- TI CDCE913, CDCE937, and CDCE949 clk generators
- Marvell Armada ap806 CPU frequencies
- STM32F4* I2S/SAI support
- Broadcom BCM2835 DSI support
- Allwinner sun5i and A80 conversion to new style clk bindings"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits)
clk: renesas: mstp: ensure register writes complete
clk: qcom: Do not drop device node twice
clk: mvebu: adjust clock handling for the CP110 system controller
clk: mvebu: Expand mv98dx3236-core-clock support
clk: zte: add i2s clocks for zx296718
clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
clk: tegra: Add BPMP clock driver
clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
clk: uniphier: add NAND clock for all UniPhier SoCs
ARM: dts: sun9i: Switch to new clock bindings
clk: sunxi-ng: Add A80 Display Engine CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
clk: qcom: SDHCI enablement on Nexus 5X / 6P
...
Driver updates for ARM SoCs.
A handful of driver changes this time around. The larger changes are:
- Reset drivers for hi3660 and zx2967
- AHCI driver for Davinci, acked by Tejun and brought in here due to
platform dependencies
- Cleanups of atmel-ebi (External Bus Interface)
- Tweaks for Rockchip GRF (General Register File) usage (kitchensink misc
register range on the SoCs)
- PM domains changes for support of two new ZTE SoCs (zx296718 and zx2967)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYrM7/AAoJEIwa5zzehBx3qisP/18NwvbYvC3rMza7k+TEU66n
vuEF9KW5GhUpQPbNIsTer5qHhC7ZgL7RoR/H7mpZcCxfhYiNXuUaOv8TMGK+WTLQ
HH6QTs4mARLh1IrRcog1hoElzzqMVxaQgODeaaG1DcPvTqHWsQurbXsf17tCQOri
nWKyxFpLNlu0kktkGb5JWrM4XBjU9KsW7LME9H86wG8HmB6+mcT5ddeYwW5nD8cG
txXgmMjdTEKcpbeTg3cAzL4504auhIl4R9uK+8dc1sw+e9T0nXNDS9IkmLPwWtSR
u8q6zQ3zReoDw4jGUgPP0ILHudfQsiMdWS+P2hw/krpbtLlQ+irHDVa1VA3NLiUT
9aG9cNTYRMo3ct22YEeWsnAC04XOxpCsqHTR+UWuZaBmf3eoMIXnsafTuwLzqKlQ
Ent/4eFPInMAzDH8Kaf1Hh0918qkgF2bNlshem11TccQKvHP+qCoHk6mKGxwEj5k
E1UEG4S6k6zNqjLwmTBBbk8sLMl/WVo6RMSMz+JflatgPmVZco4EX2O73iKGAJVU
5GfHIUG9Yl4+aTIUORu59cWxOCApK0kqERrFKe412BMurXlLfqVcr/H2tiiuWnn1
cEJ9d+uBd8IxTIQX0iEYGUAkX97mhxGUYdqGQuGJSV+MOfWX1zNP1sI4EscLGKQj
sDDZScCaguM4xE20Jum1
=od7u
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs.
A handful of driver changes this time around. The larger changes are:
- Reset drivers for hi3660 and zx2967
- AHCI driver for Davinci, acked by Tejun and brought in here due to
platform dependencies
- Cleanups of atmel-ebi (External Bus Interface)
- Tweaks for Rockchip GRF (General Register File) usage (kitchensink
misc register range on the SoCs)
- PM domains changes for support of two new ZTE SoCs (zx296718 and
zx2967)"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
soc: samsung: pmu: Add register defines for pad retention control
reset: make zx2967 explicitly non-modular
reset: core: fix reset_control_put
soc: samsung: pm_domains: Read domain name from the new label property
soc: samsung: pm_domains: Remove message about failed memory allocation
soc: samsung: pm_domains: Remove unused name field
soc: samsung: pm_domains: Use full names in subdomains registration log
sata: ahci-da850: un-hardcode the MPY bits
sata: ahci-da850: add a workaround for controller instability
sata: ahci: export ahci_do_hardreset() locally
sata: ahci-da850: implement a workaround for the softreset quirk
sata: ahci-da850: add device tree match table
sata: ahci-da850: get the sata clock using a connection id
soc: samsung: pmu: Remove duplicated define for ARM_L2_OPTION register
memory: atmel-ebi: Enable the SMC clock if specified
soc: samsung: pmu: Remove unused and duplicated defines
memory: atmel-ebi: Properly handle multiple reference to the same CS
memory: atmel-ebi: Fix the test to enable generic SMC logic
soc: samsung: pm_domains: Add new Exynos5433 compatible
soc: samsung: pmu: Add dummy support for Exynos5433 SoC
...
ARM64 DT updates are fairly small this time, only two new SoCs and a handful
of new machines get added, all of them similar to other hardware we already
support.
New SoC:
- HiSilicon Kirin960/Hi3660 and HiKey960 development board
- NXP LS1012a with three reference boards
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A
New development board:
- Banana Pi M64, based on Allwinner A64
http://www.banana-pi.org/m64.html
- SolidRun MACCHIATOBin based on Marvell Armada 8K
https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/
- Broadcom BCM958712DxXMC NorthStar2 reference board (another one)
A lot of platforms improve support for existing machines by adding
extra devices for which a binding and driver is availabe:
Allwinner: MMC, USB
ARM Juno: Coresight, STM
Broadcom: NS2 GICv2m irqchip and PCIe
Marvell: Armada 3700 SPI, I2C, ethernet switch
Mediatek: MT8173 thermal
NXP i.MX: LS1046A thermal
Qualcomm: coresight on MSM8916, HDMI, WCNSS, SCM
Renesas: r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd
Rockchip: thermal, eDP, pinctrl enhancements
Samsung: TM2 touchkey, Exynos5433 HDMI and power management improvements
UniPhier: SD reset, eMMC controller
ZTE: oppv2 cpufreq
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIUAwUAWK9htWCrR//JCVInAQL5sg/40ehZk89xuReYHaOoL0jkEGxt7ogae2Q0
5SurlVNEjkr1A6KKcTKwy6c8E4GReq0ioVUxyYHlNo2MedtLQWssSvObfjt390E+
OYXhuHHyHFgut9jF6nq1IZbSqkhaDcoRFdK0EPzjdxTMMk59xqzG2t9Kbq0MFz0I
Fg0+xB44VAOwuM+45MjNzdpTzolkH3gxlK4TV/opbr2/9uEDCjFOLr1zqZuWqIDh
uyXXqHYUZ54kz2GvhfYPgcm+f+PjuV2fw/Jh5u3+jNvwMQvA70Erv52im1o1a3GV
UTjmBgccTKByrPk7gXP3lgRkHQGwPLNH0L+28AZ/BNuZbWqDrDe7uVfpq9nWb5Xl
IR0uleNBOuiOdqR6Ya4xosGSm6AOgQhCbE52trHdUhb03eqRbqHcLHEVmZXXea/i
EejGOciIvbV8ent9jjREw/kvGZ+Ws6v5notG4uPDwn+YZSJAyqvGh5Tul8WzZIxk
Wr1WZgbuwkI0KYiFzSINfgDX0Om2l6YoVZLnkjst5Exto+TGRSINJpVCXsuGIU7O
34qZD25yA8WlJTooBL0cvrW0NT2RewBqLogwhbwDnRW241SW5AnuzPsFPWldLzon
L5sFgsF60gWiIlbB2/BKdpF2jB/+brXNR6epnQYADigweg/4+pS8HPZRFj7g8wyE
s22+OYJ6Cg==
=glug
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"ARM64 DT updates are fairly small this time, only two new SoCs and a
handful of new machines get added, all of them similar to other
hardware we already support.
New SoC:
- HiSilicon Kirin960/Hi3660 and HiKey960 development board
- NXP LS1012a with three reference boards:
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/qoriq-layerscape-arm-processors/qoriq-layerscape-1012a-low-power-communication-processor:LS1012A
New development board:
- Banana Pi M64, based on Allwinner A64:
http://www.banana-pi.org/m64.html
- SolidRun MACCHIATOBin based on Marvell Armada 8K:
https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/
- Broadcom BCM958712DxXMC NorthStar2 reference board (another one)
A lot of platforms improve support for existing machines by adding
extra devices for which a binding and driver is availabe:
Allwinner:
- MMC, USB
ARM Juno:
- Coresight, STM
Broadcom:
- NS2 GICv2m irqchip and PCIe
Marvell:
- Armada 3700 SPI, I2C, ethernet switch
Mediatek:
- MT8173 thermal
NXP i.MX:
- LS1046A thermal
Qualcomm:
- coresight on MSM8916, HDMI, WCNSS, SCM
Renesas:
- r8a779[56] thermal, powerdomain, ethernet, sound, pwm, can, can fd
Rockchip:
- thermal, eDP, pinctrl enhancements
Samsung:
- TM2 touchkey, Exynos5433 HDMI and power management improvements
UniPhier:
- SD reset, eMMC controller
ZTE:
- oppv2 cpufreq"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (110 commits)
arm64: dts: qcom: Add msm8916 CoreSight components
arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
arm64: allwinner: add BananaPi-M64 support
arm64: allwinner: a64: add UART1 pin nodes
arm64: allwinner: pine64: add MMC support
arm64: allwinner: a64: Increase the MMC max frequency
arm64: allwinner: a64: Add MMC pinctrl nodes
arm64: allwinner: a64: Add MMC nodes
dt-bindings: clockgen: Add compatible string for LS1012A
Documentation: DT: add LS1012A compatible for SCFG and DCFG
Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boards
arm64: dts: marvell: add generic-ahci compatibles for CP110 ahci
arm64: tegra: Use symbolic reset identifiers
arm64: dts: r8a7796: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: tidyup audma definition order
arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
arm64: dts: r8a7796: Add R-Car Gen3 thermal support
arm64: dts: r8a7795: Add R-Car Gen3 thermal support
...
A total of 380 patches this time, mostly adding support for more hardware
in the device tree descriptions. There is not much exciting here for 4.11,
but I've tried my best to condense the information from the pull requests
I got into a readable summary.
Noteworthy changes to existing platforms include:
- The GIC memory map was a bit wrong almost everywhere and now
gets fixed up
- The Allwinner platforms convert to the generic pinmux properties
- The Marvell EBU platforms now use the new DSA binding
- Samsung Exynos4212 was unused and gets removed
- The Renesas power management got improved
New production machines:
- Lego Mindstorms EV3
https://www.lego.com/en-us/mindstorms/about-ev3
- Beelink X2 Android media box
http://linux-sunxi.org/Beelink_X2
- "Romulus" baseboard management controller for OpenPower
- Axentia TSE-850 Data Radio Channel (DARC) encoder
http://www.axentia.se/db/equipment.html
- Luxul XAP-1410 and XWR-1200 wireless access points
https://luxul.com/xap-1410
New SoCs:
- Allwinner H2+ and V3s, both minor variations of already
supported chips
http://www.allwinnertech.com/index.php?c=product&a=index&id=38
- Marvell Prestera DX packet processors based on Armada XP architecture
http://www.marvell.com/switching/prestera-dx/
- Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412
New developer and reference boards:
- Lichee Pi One, Lichee Pi Zero and Orange Pi Zero,
all based on Allwinner SoCs
http://linux-sunxi.org/LicheePi_Onehttp://www.orangepi.org/orangepizero/
- SAMA5d36ek Reference platform
http://www.atmel.com/tools/sama5d36-ek.aspx
- Beaglebone Green Wireless and Black Wireless
https://beagleboard.org/black-wirelesshttps://beagleboard.org/green-wireless
- phyCORE-AM335x System on Module
http://phytec.com/products/system-on-modules/phycore/am335x/
- New revision of "vf610-zii" Zodiac Inflight Innovations board
- Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core
http://www.opossom.com/english/index.htmlhttp://www.savageboard.org/http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ulhttp://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
- Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is
Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom,
rockchip, sti, stm32 and tegra
New device supports added to some boards and SoCs, briefly by platform:
- Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU
- Aspeed: network, ipmi bt, gpio, pinmux
- Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc
- TI DaVinci: gpio, lcdc, usb, video-in, uart
- TI Keystone 2: MSM RAM, power/reset, uart
- Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal
- Marvell EBU: ethernet switch on Turris Omnia
- NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic,
eeprom, mmc, nand
- TI OMAP:
- Qualcomm: coresight, gyro/accelerometer, hdmi
- Renesas: pmic, soc-id
- Rockchip: qos
- Samsung: audio on Odroid-X
- Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor
- STi: video in/out
- STM32: timer, pwm, i2c, rtc, add, i2s
- NVIDIA Tegra: tpm
- Uniphier: mmc/sd pinmux
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAWK9aamCrR//JCVInAQJPpBAA2qUQYRfCgzK1fEu6X+c8pzqITqlV+Hx7
8tBsZFINywKLnUXLs4Ip4DDK8uDsIACXSmGMdmhUVIXLsuRxJBl8av+ndd+ERGoF
bg/iAIyA9hjKRhorE1wDyC4wg1S4P8laPevbK7NcDYDbK9MRmGSmEyP2uvhfLtVy
2zoPfIE5aEipx6GoIATzLRqpMO6rWB/eg9OUZVKN5Hwh3LNCKtkX726GC9WGVqoE
zslF1S6VH63dfru2Vlu5eFdvmiox54gBJBMR7yld+EIiXWilNT0eWfEYRd3CMT6E
EwRCNiNRa21DHstBdL9pTuE+K0LpAUXlznjiqeWrZVuJfdHJy51pGVWwoc4ynbhI
TS/GFgJI4iG2xrE3EIJS5cAl1S9WtNOYYvZATM35blFbZv7ASoAGdj2EECIIPwJr
CR4l9Y2k/fuNHAzhR4B0fEKj/uWj7ONqcolpf8W6lZx0MvVNgeDwdx0eoLrbrxY9
MJFb9OgD+BhNp5lIElysl0L9aEp3PxV668nSg4qV+Mo4w/5/OXhHK8675bXlITFU
4Rw6fxRUBeO2B0LSonE4Ds8QKMQCs2yfxyMPWMn8yK/xFkwpHzwoJuRR2RYpbQTb
5Hrnfk23k+2rflht07XBxNqqaznDQyPPvAvoB0ZZ2kchPYl75MlpAfOGlgfhXcmm
Kp4g7VYyfAs=
=ucQ/
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"A total of 380 patches this time, mostly adding support for more
hardware in the device tree descriptions. There is not much exciting
here for 4.11, but I've tried my best to condense the information from
the pull requests I got into a readable summary.
Noteworthy changes to existing platforms include:
- The GIC memory map was a bit wrong almost everywhere and now gets
fixed up
- The Allwinner platforms convert to the generic pinmux properties
- The Marvell EBU platforms now use the new DSA binding
- Samsung Exynos4212 was unused and gets removed
- The Renesas power management got improved
New production machines:
- Lego Mindstorms EV3:
https://www.lego.com/en-us/mindstorms/about-ev3
- Beelink X2 Android media box:
http://linux-sunxi.org/Beelink_X2
- "Romulus" baseboard management controller for OpenPower
- Axentia TSE-850 Data Radio Channel (DARC) encoder:
http://www.axentia.se/db/equipment.html
- Luxul XAP-1410 and XWR-1200 wireless access points:
https://luxul.com/xap-1410
New SoCs:
- Allwinner H2+ and V3s, both minor variations of already supported
chips:
http://www.allwinnertech.com/index.php?c=product&a=index&id=38
- Marvell Prestera DX packet processors based on Armada XP
architecture:
http://www.marvell.com/switching/prestera-dx/
- Samsung Exynos4412 Prime gets added, a minor variation of
Exynos4412
New developer and reference boards:
- Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on
Allwinner SoCs:
http://linux-sunxi.org/LicheePi_Onehttp://www.orangepi.org/orangepizero/
- SAMA5d36ek Reference platform:
http://www.atmel.com/tools/sama5d36-ek.aspx
- Beaglebone Green Wireless and Black Wireless:
https://beagleboard.org/black-wirelesshttps://beagleboard.org/green-wireless
- phyCORE-AM335x System on Module:
http://phytec.com/products/system-on-modules/phycore/am335x/
- New revision of "vf610-zii" Zodiac Inflight Innovations board
- Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam
i.Core:
http://www.opossom.com/english/index.htmlhttp://www.savageboard.org/http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ulhttp://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q
- Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is
- Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas,
qcom, rockchip, sti, stm32 and tegra
New device supports added to some boards and SoCs, briefly by platform:
- Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU
- Aspeed: network, ipmi bt, gpio, pinmux
- Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc
- TI DaVinci: gpio, lcdc, usb, video-in, uart
- TI Keystone 2: MSM RAM, power/reset, uart
- Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal
- Marvell EBU: ethernet switch on Turris Omnia
- NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom,
mmc, nand
- TI OMAP:
- Qualcomm: coresight, gyro/accelerometer, hdmi
- Renesas: pmic, soc-id
- Rockchip: qos
- Samsung: audio on Odroid-X
- Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor
- STi: video in/out
- STM32: timer, pwm, i2c, rtc, add, i2s
- NVIDIA Tegra: tpm
- Uniphier: mmc/sd pinmux"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits)
ARM: dts: armada-385-linksys: fix DSA compatible property
ARM: dts: Fix typo in armada-xp-98dx4251
ARM: DTS: Fix register map for virt-capable GIC
dt-bindings: arm,gic: Fix binding example for a virt-capable GIC
ARM: dts: sun8i: sinlinx: Enable audio nodes
ARM: dts: sun8i: parrot: Enable audio nodes
ARM: dts: sun8i: Add audio codec, dai and card for A33
ARM: dts: Add EMAC AXI settings for Arria10
ARM: dts: am335x-chiliboard: Support charger
ARM: dts: am335x-chiliboard: Support power button
ARM: sun8i: dt: Add mali node
dt-bindings: gpu: Add Mali Utgard bindings
ARM: dts: stm32: Add I2C1 support for STM32429 eval board
ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
ARM: dts: stm32: Use clock DT binding definition on stm32f429 family
dt-bindings: mfd: stm32f4: Add missing binding definition
dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro
ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
ARM: dts: stm32: add Timers driver for stm32f429 MCU
ARM: dts: add the AB8500 sysclk to the device trees
...
We sometimes collect non-critical fixes that come in during the later part
of the merge window in a branch for the next release instead, and this is
that contents for v4.11.
Most of these are OMAP fixes, dealing with OMAP36/37 detection, quirks
and setup. There's also some fixes for Davinci and a Kconfig fix for SCPI
to only enable on ARM{,64}.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYrMlHAAoJEIwa5zzehBx3oZ4P/3nRgb4dtwEwXwFmJf8Xd4nu
yetQbcwRreHvh8utsU2Pe+8tffV8jLgsW8TxZ43d6deYFii046HhZAXtvTTVgFpE
OA0fJpNJ00KYqP1Nx5q/kwZoH3uBz442uMUQ9lyziB3RpimhRsiKyHwnTyuWljyx
hPmO1XKcF6pQBXk1uwOzO1lSDUeOn4eAmeLonlG1gQ5qtrkU0WbrTPxpmn/CB546
LH5Nj0qVRzEa7xr8O+2nzeKPVwcXGwsKVKCDbSJmsey2KOEDnEjjxpToAh3WnA4W
Tm1av5QdyqsLVqAMkNYezrS8EzBjRKa1ma4xUqsNoIhO1XI7xa/LkonU8a0+ZdSX
p48DCvv7IHX5IqdIHHB0s1eICvTsW8Cp/4YUJzuZDFbS9B2t5b3412+n43tVa8l3
HYPeTzL5S3VOrMtpQKkGAFrw5OGm+URy4CYQxpX5DxSRSqvXTj12ajBHRbfdbzCO
r2i2rhKL07PF3DAf8L1coHcBQDS7Vc/k+fhKCQy+W1RDxmjYwYKSI9agOyZi1HQ7
X+0HuUyKTthCE2kUrj4rye/87MffWwdjNgnOZiHR1X7YtWgnjp1g9K+mLZHh/y5m
Tq/M55cK9h6dOghx121jYFkkvDclEQDemJuDbKY0sEMDrDXtppcI/T+znZ1LTq7i
1eaK4lTyAX7dbQJUQCwe
=NhZq
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-urgent fixes from Arnd Bergmann:
"We sometimes collect non-critical fixes that come in during the later
part of the merge window in a branch for the next release instead, and
this is that contents for v4.11.
Most of these are OMAP fixes, dealing with OMAP36/37 detection, quirks
and setup. There's also some fixes for Davinci and a Kconfig fix for
SCPI to only enable on ARM{,64}"
* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
firmware: arm_scpi: Add hardware dependencies
ARM: OMAP3: Fix SoC detection of OMAP36/37 Family
ARM: OMAP5: Add HWMOD_SWSUP_SIDLE_ACT flag for UART
ARM: dts: Fix compatible for ti81xx uarts for 8250
ARM: dts: Fix am335x and dm814x scm syscon to probe children
ARM: OMAP2+: Fix init for multiple quirks for the same SoC
ARM: dts: Fix omap3 off mode pull defines
bus: da850-mstpri: fix my e-mail address
ARM: davinci: da850: fix da850_set_pll0rate()
ARM: davinci: da850: coding style fix
Pull networking updates from David Miller:
"Highlights:
1) Support TX_RING in AF_PACKET TPACKET_V3 mode, from Sowmini
Varadhan.
2) Simplify classifier state on sk_buff in order to shrink it a bit.
From Willem de Bruijn.
3) Introduce SIPHASH and it's usage for secure sequence numbers and
syncookies. From Jason A. Donenfeld.
4) Reduce CPU usage for ICMP replies we are going to limit or
suppress, from Jesper Dangaard Brouer.
5) Introduce Shared Memory Communications socket layer, from Ursula
Braun.
6) Add RACK loss detection and allow it to actually trigger fast
recovery instead of just assisting after other algorithms have
triggered it. From Yuchung Cheng.
7) Add xmit_more and BQL support to mvneta driver, from Simon Guinot.
8) skb_cow_data avoidance in esp4 and esp6, from Steffen Klassert.
9) Export MPLS packet stats via netlink, from Robert Shearman.
10) Significantly improve inet port bind conflict handling, especially
when an application is restarted and changes it's setting of
reuseport. From Josef Bacik.
11) Implement TX batching in vhost_net, from Jason Wang.
12) Extend the dummy device so that VF (virtual function) features,
such as configuration, can be more easily tested. From Phil
Sutter.
13) Avoid two atomic ops per page on x86 in bnx2x driver, from Eric
Dumazet.
14) Add new bpf MAP, implementing a longest prefix match trie. From
Daniel Mack.
15) Packet sample offloading support in mlxsw driver, from Yotam Gigi.
16) Add new aquantia driver, from David VomLehn.
17) Add bpf tracepoints, from Daniel Borkmann.
18) Add support for port mirroring to b53 and bcm_sf2 drivers, from
Florian Fainelli.
19) Remove custom busy polling in many drivers, it is done in the core
networking since 4.5 times. From Eric Dumazet.
20) Support XDP adjust_head in virtio_net, from John Fastabend.
21) Fix several major holes in neighbour entry confirmation, from
Julian Anastasov.
22) Add XDP support to bnxt_en driver, from Michael Chan.
23) VXLAN offloads for enic driver, from Govindarajulu Varadarajan.
24) Add IPVTAP driver (IP-VLAN based tap driver) from Sainath Grandhi.
25) Support GRO in IPSEC protocols, from Steffen Klassert"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1764 commits)
Revert "ath10k: Search SMBIOS for OEM board file extension"
net: socket: fix recvmmsg not returning error from sock_error
bnxt_en: use eth_hw_addr_random()
bpf: fix unlocking of jited image when module ronx not set
arch: add ARCH_HAS_SET_MEMORY config
net: napi_watchdog() can use napi_schedule_irqoff()
tcp: Revert "tcp: tcp_probe: use spin_lock_bh()"
net/hsr: use eth_hw_addr_random()
net: mvpp2: enable building on 64-bit platforms
net: mvpp2: switch to build_skb() in the RX path
net: mvpp2: simplify MVPP2_PRS_RI_* definitions
net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT
net: mvpp2: remove unused register definitions
net: mvpp2: simplify mvpp2_bm_bufs_add()
net: mvpp2: drop useless fields in mvpp2_bm_pool and related code
net: mvpp2: remove unused 'tx_skb' field of 'struct mvpp2_tx_queue'
net: mvpp2: release reference to txq_cpu[] entry after unmapping
net: mvpp2: handle too large value in mvpp2_rx_time_coal_set()
net: mvpp2: handle too large value handling in mvpp2_rx_pkts_coal_set()
net: mvpp2: remove useless arguments in mvpp2_rx_{pkts, time}_coal_set
...
Core changes:
- Switch the generic pin config argument from 16 to 24 bits,
only use 8 bits for the configuration type. We might need to
encode more information about a certain setting than we need
to encode different generic settings.
- Add a cross-talk API to the pin control GPIO back-end,
utilizing pinctrl_gpio_set_config() from GPIO drivers that
want to set up a certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the
GPIO chips, so that they pass a generic configuration for
things like debouncing and single ended (typically open
drain). This change has also been merged in an immutable
branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing
a pin controller before trying to get any hogs.
- For pin controllers putting all group and function definitions
into the device tree, we now have generic code to deal with
this and it is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down.
New subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in
the LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on
GPIOs. Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode.
STM32H743 MCU support.
- Allwinner sunxi: deep simplifications on how to support
subvariants of SoCs without adding to much SoC-specific data
for each subvariant, especially for sun5i variants. New driver
for V3s SoCs. New driver for the H5 SoC. Support A31/A31s
variants with the new variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction.
New subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the
SoC driver to access regmaps. Add infrastructure for pin-bank
retention control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly
in the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm
driver realtime-safe.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJYq/7kAAoJEEEQszewGV1zf4oQALVaN5tuaCbzN4QOq87jzXmk
K195kKG0nkNvN6o5llNhBszHfCSmX1+oSscxuCF/88kH4mFHeDIbvg0KOk5IZYxA
YlT8NA75C9+flARE3gQUyL320ulahWbvOthntQprzsVU4RJa0zP38peQsfiUd8W1
ch8GInJYYkczcsAbmziyUOBu5a2o9tX3u8BF8FaBf2uyrCiBC/ZT2VpzvbOR5NeU
MvjFvc7bq2fNltzDNHdZZUo/5iCbnPlRNig2umDp5fFa8rZcdPmGMAOl4p6nizHY
S16xDl38xxDQx8sp1IH4n+th3G2cXoONEj9eZ6woWTJhLbLc13CacYPfleYfqEOe
+JyrUgBgFBINiFWDHHaebWJeD2M/QF4FnSDGnnJBy/bKWe6lJnknGvSZNcIEvdvB
QeeKyfrvnKiCyjNY4N+ZNdMLA2vj5o86vG2hSqztPiwYWDePbN76yeZ7l79bFfOo
ZnCa2ay70Np7xwrQWors4Gl2LV2zJG7AkaNA7vvS9NX6OURu/SkNVePkY1XHCLwu
lNvYd4iwFJxzXm08TsgtLC080eZfvCot9xqbgzvoapnwx7tBuaAakXI4bh0T3x4n
pEauKO3oNE/K89mN9QK2jfsD9kDWvm4xvc+ilA6DGU0C37XnDQjF+Q5xy16262Gh
9w0yWMlqzrr7stUXAjS4
=IMY0
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Pin control bulk changes for the v4.11 kernel cycle.
Core changes:
- Switch the generic pin config argument from 16 to 24 bits, only use
8 bits for the configuration type. We might need to encode more
information about a certain setting than we need to encode
different generic settings.
- Add a cross-talk API to the pin control GPIO back-end, utilizing
pinctrl_gpio_set_config() from GPIO drivers that want to set up a
certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the GPIO chips,
so that they pass a generic configuration for things like
debouncing and single ended (typically open drain). This change has
also been merged in an immutable branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing a pin
controller before trying to get any hogs.
- For pin controllers putting all group and function definitions into
the device tree, we now have generic code to deal with this and it
is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down. New
subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in the
LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode. STM32H743 MCU
support.
- Allwinner sunxi: deep simplifications on how to support subvariants
of SoCs without adding to much SoC-specific data for each
subvariant, especially for sun5i variants. New driver for V3s SoCs.
New driver for the H5 SoC. Support A31/A31s variants with the new
variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction. New
subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
driver to access regmaps. Add infrastructure for pin-bank retention
control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm driver
realtime-safe"
* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
pinctrl: intel: unlock on error in intel_config_set_pull()
pinctrl: berlin: make bool drivers explicitly non-modular
pinctrl: spear: make bool drivers explicitly non-modular
pinctrl: mvebu: make bool drivers explicitly non-modular
pinctrl: sunxi: make sun5i explicitly non-modular
pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
pinctrl: samsung: mark PM functions as __maybe_unused
pinctrl: sunxi: Remove redundant A31s pinctrl driver
pinctrl: sunxi: Support A31/A31s with pinctrl variants
pinctrl: Amend bindings for STM32 pinctrl
pinctrl: Add STM32 pinctrl driver DT bindings
pinctrl: stm32: Add STM32H743 MCU support
include: dt-bindings: Add STM32H7 pinctrl DT defines
gpio: aspeed: Remove dependence on GPIOF_* macros
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
drivers: pinctrl: add driver for Allwinner H5 SoC
pinctrl: intel: Add Intel Gemini Lake pin controller support
pinctrl: intel: Add support for 1k additional pull-down
pinctrl: intel: Add support for hardware debouncer
...
- new driver for stts751
- it87: Added support for IT8622E and IT8792E; improved support for other chips
- lm70: Added support for TMP122/124
- use permission-specific DEVICE_ATTR variants where possible
- fixed overflows in various drivers
- minor improvements in various drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYqmJwAAoJEMsfJm/On5mBeGoP/0eUxc3crX3vcJrbPwLnvnZ0
n90QIoe0Dk/699lHUu8K098Ihsj3mxOXqDgx7YTPHi3MdekoL0KkYZn/yyvE+wX/
dcB+gz02/WLUBoUoA6rhbztqLFC59Iv4TwxGFMSU//ySGRzmy/0AZ/sG5h8C+Fli
05+b4BdOZGSqff3EBHKJSzLrzYmbMq4+f0JlpUCNIve8gfgomenwfbrghEJw6VAj
xp9EKM5KBLLj4e76Muk42FEvD7TxdbLeXoj/g+Tz6w8seWmQAyRinu6Udn7FqPOQ
an/2QrtQfGgWEuZ/QbsZN9mneou4EJq4SvvUUtHLgDj6zF5mnHla/nSc62l//uac
QVeTKCxh5/A7y+QzeQFZ/zI/5/oVQICrx5K+VCPnkH33c2DcsElBtsQaA+Jk8RNy
S9C3UN+bAfR/SWpOiKjSu/VE3OgHzQm+TZKXyfMOGSmX+hJZcuROTNuvAso6fvVQ
mmKtfbA+POG9DNvrHpu2ohzc42HXfAExrnclF3AxuIMHb6Qt5cwpQMgGt4Yk/CFa
aOWX2oQPnSbx2qzhlAZdo34fflGYMf4DvsMBYc6e/6vY0WHLnL3IyfWOlw3Yrdpu
/rjgheQb5vjoRvPadBJphFSRF4xzZCIkP+ue9o0EEqPhsJjnWmwuHhr97CaO4ror
dJDtXi+i67uuti/NsqYP
=QLmt
-----END PGP SIGNATURE-----
Merge tag 'hwmon-for-linus-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
Pull hwmon updates from Guenter Roeck:
- new driver for stts751
- it87: Added support for IT8622E and IT8792E; improved support for
other chips
- lm70: Added support for TMP122/124
- use permission-specific DEVICE_ATTR variants where possible
- fixed overflows in various drivers
- minor improvements in various drivers
* tag 'hwmon-for-linus-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: (95 commits)
hwmon: (sht15) Add device tree support
devicetree: add lm90 thermal_zone sensor support
hwmon: (it87) Add support for IT8792E
hwmon: (it87) Do not overwrite bit 2..6 of pwm control registers
hwmon: (it87) Fix pwm4 detection for IT8620 and IT8628
hwmon: (it87) Ensure that pwm control cache is current before updating values
hwmon: (it87) Improve IT8622 support
hwmon: (it87) Add support for IT8622E
hwmon: (it87) Add feature flag indicating that VIN3 is connected to 5V
DT: add binding documentation for STTS751
hwmon: new driver for ST stts751 thermal sensor
hwmon: Register thermal zone only if 'dev' parameter was provided
hwmon: Relax name attribute validation for new APIs
hwmon: Update documentation to clarify rules for the 'name' attribute
hwmon: Make name attribute mandatory for new APIs
hwmon: (lm70) Add support for TI TMP122/124
hwmon: (lm70) Utilize dev_warn instead of pr_warn
hwmon: (ltc4151) Export OF device ID table as module aliases
hwmon: (adc128d818) Preserve operation mode
hwmon: (adc128d818) Support operation modes 1-3
...
1. Add necessary initial configuration for clocks of display subsystem.
Till now it worked mostly thanks to bootloader.
2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7.
3. Enable USB 3.0 (DWC3) on Exynos7.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYk3YaAAoJEME3ZuaGi4PXYwAP/2d7SiLymurXwmctrxm9Q5kI
ZD7xdTr5JWq/sbuGfDHLKUz4iPMBsdQqRwczZ+DSls+Iet1fNw4enmoU/p1SpZ/5
31EFB3uN28DSL4ZA3SzOrzPgcdMRxXOYhUMq9DTY5N8h0LlI2TwB3WBDgWTpGB6R
NXX3wKulH2hXJyOizOZh2yel5KvzLqug7j/V0u9K1OmUISmTy3XfDWaXIVk33MUw
IZ6qpgTzShw6sZj5VmR9CFPFbDjwExTVenIA9gwewJlQNQnqrsg0BdEF3ZvasW+V
eFeLV4ieZHKzEoVjwdxGgTLLwjjL/orsWQ5CYiQNeCKC85rgTVfijTe8s+QKOYAq
SiV1GghHACExpCULhtQiqioFsUAUPJ+iq/EZ9NfNh7QzE5Y05RJ7bRgRd2UdBlN8
BXhekgN5RepLwKWHK8oYivMMpIKzDve1ICRpQYBVxmmwg9nzRz6Nij2YUi4oEb5j
77FOuyKe5M+QCIoKVn2v/CDQMemGkI8OEsKubjDKcOZ2V2COw7Sr1L/GCGVCslLM
FyOjaTKeoIzkrx62qgqGFuNwEaZwW0dDacHrZrccEAn9P9G7O/cU8EE9F5nJqGG0
IeDaPH7BqQ0gOHbvrEkljSbJuuOMQmZJl6qh8MMJYB9P8u9Ft3OXUXJ1qBNZB4si
E5nFWGj0CMm0UfBWgkD/
=02Sx
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late
Pull "Samsung DeviceTree ARM64 update for v4.11, third round" from Krzysztof Kozłowski:
1. Add necessary initial configuration for clocks of display subsystem.
Till now it worked mostly thanks to bootloader.
2. Use macro definitions instead of hard-coded values for pinctrl on Exynos7.
3. Enable USB 3.0 (DWC3) on Exynos7.
* tag 'samsung-dt64-4.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (27 commits)
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
arm64: dts: exynos: set LDO7 regulator as always on
arm64: dts: exynos: configure TV path clocks for Ultra HD modes
arm64: dts: exynos: Fix drive strength of sd0_xxx pin definitions
arm64: dts: exynos: Disable pull down for audio pins in Exynos5433 SoCs
arm64: dts: exynos: Add TM2 touchkey node
arm64: dts: exynos: Remove unneeded unit names in Exynos5433 nodes
arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2
arm64: dts: exynos: Add HDMI node to Exynos5433
arm64: dts: exynos: Add DECON_TV node to Exynos5433
arm64: dts: exynos: Fix addresses in node names on Exynos5433
arm64: dts: exynos: Make TM2 and TM2E independent from each other
arm64: dts: exynos: Fix wrong values for ldo23 and ldo25 on TM2/TM2E
...
This patch updates the LM90's devicetree definition to
include the #thermal-sensor-cells property as well as
the sensor constants in include/dt-bindings/thermal/lm90.h.
Cc: Wei Ni <wni@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
LED Mode:
Microsemi PHY support 2 LEDs (LED[0] and LED[1]) to display different
status information that can be selected by setting LED mode.
LED Mode parameter (vsc8531, led-0-mode) and (vsc8531, led-1-mode) get
from Device Tree.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>