7 Commits

Author SHA1 Message Date
Peter Ujfalusi
a571cb17ac ASoC: tas2552: Configure the WCLK frequency based on the stream
Instead of hard wiring the WCLK frequency at probe time do it runtime.
The hard wired 88_96KHz was not even setting the correct bits since it was
defined as (1 << 6) which will  change the I2S_OUT_SEL bit and will leave
the amplifier configured for 8KHz.
At the same time clean up and fix the CFG3 register bits.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:36 +01:00
Peter Ujfalusi
d20b098dd9 ASoC: tas2552: Add support for word length configuration
Configure the word length based on the params_width of the stream.
Also configure the clock per frame value which is used when tas2552 is bus
master.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:36 +01:00
Peter Ujfalusi
3f747a810e ASoC: tas2552: Add TDM support
TDM support is achieved using DSP transfer mode and setting a programmable
offset which specifies where data begins with respect to the frame sync.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:34 +01:00
Peter Ujfalusi
1b68c7dca2 ASoC: tas2552: Correct and clean up data format and BCLK/WCLK direction
Use names from the datasheet for the definitions.
Correct the data format definitions since they were not correct.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:34 +01:00
Peter Ujfalusi
7de544fd32 ASoC: tas2552: Correct CFG1 register bit definitions
Remove the _MASK postfix of the bit definitions, collect the CFG1 bit
definition in one place and correct the bit shifts at the same time.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-04 17:50:02 +01:00
Peter Ujfalusi
89683fdefd ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.

The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-04 17:50:02 +01:00
Dan Murphy
5df7f71d5c ASoC: tas2552: Support TI TAS2552 Amplifier
Support the TI TAS2552 Class D amplifier.

The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
The device constantly measures the
current and voltage across the load and provides a
digital stream of this information.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-17 17:57:05 +01:00