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4 Commits

Author SHA1 Message Date
Noam Camus
09dcd1958b soc: Support for NPS HW scheduling 
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.

Signed-off-by: Noam Camus <noamca@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
 2016-11-30 11:54:25 -08:00
Noam Camus
66619433d0 ARC: [plat-eznps] remove IPI clear from SMP operations 
Today we register to plat_smp_ops.clear() method which actually
is acking the IPI.
However this is already taking care by our irqchip driver specifically
by the irq_chip.irq_eoi() method.
This is perfect timing where it should be done and no special handling
is needed at plat_smp_ops.clear().

Signed-off-by: Noam Camus <noamca@mellanox.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
 2016-11-08 09:25:18 -08:00
Noam Camus
86c25466f7 ARC: [plat-eznps] Use dedicated identity auxiliary register. 
With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.

Signed-off-by: Noam Camus <noamc@ezchip.com>
 2016-05-09 09:32:33 +05:30
Noam Camus
4a66d3fecf ARC: [plat-eznps] Add eznps platform 
This platform include boards:
	Hardware Emulator (HE)
	Simulator based upon nSIM.

Signed-off-by: Noam Camus <noamc@ezchip.com>
 2016-05-09 09:32:32 +05:30