5 Commits

Author SHA1 Message Date
Junlin Yang
0b1f557a1f csky: Fixup typos
fixes three typos found by codespell.

Signed-off-by: Junlin Yang <yangjunlin@yulong.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-04-20 09:58:29 +08:00
Guo Ren
6607aa6f6b csky: Fixup compile error
: error: C++ style comments are not allowed in ISO C90
 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
 ^
error: (this will be reported only once per input file)

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-02-27 22:04:14 +08:00
Guo Ren
8d11f21a73 csky: Fixup barrier design
Remove shareable bit for ordering barrier, just keep ordering
in current hart is enough for SMP. Using three continuous
sync.is as PTW barrier to prevent speculative PTW in 860
microarchitecture.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-01-12 09:52:40 +08:00
Guo Ren
81b23ba645 csky: Fixup mb() synchronization problem
The mb() is the superset of dma and smp. Using bar.xxx to implement
mb() will cause problem when sync data with dma device, becasue
bar.xxx couldn't guarantee bus transactions finished at outside bus
level.

We must use sync.s instead of bar.xxx for dma data synchronization
and it will guarantee retirement after getting the bus bresponse.

Changes for V2:
 - Use sync.s for all mb, rmb, wmb, dma_wmb, dma_rmb.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
2019-07-31 11:04:29 +08:00
Guo Ren
00a9730e10 csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2018-10-25 23:36:19 +08:00