IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
Fix the issue reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxW)
+ writel(clksel->val , cpuclk->reg_base + clksel->reg);
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Avoid return NULL if rockchip_clk_register_mmc fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Avoid return NULL if rockchip_clk_register_inverter fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rockchip_clk_get_grf pass on return value from
syscon_regmap_lookup_by_phandle, so we check grf to
make sure whether to do the following things or not.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJWuwINAAoJEPOmecmc0R2BUgMIAKmXROUpwuap5hhDv+XapDyc
drU3DmOwFQeIiaODZQVFlx8CcXUN6h/8cPZnc4Qd/ChO73TxfvtWY3S7n0n3F/EH
RIceQ30OHTUEYh/k449Sf/sTEOW68h4TdhaVrw2gJYKsJ5fg2ih5o6naWnWWE6Ig
WUh+xeeYdG6L8hCLcUA8sujE3EpG5kJelnWiMBedx6CbuTSSfJcB9tTkg1eOa/R+
jyBgYJJSuSEwG4mJijV61tanZw1FhWu+i4dEAGHkWgimuGekO4CEnRRczZ1hw7x2
O/cBfpLW4D2iGMlrvyUhcB/pe/TmRdz4SfzDSTwLPtpCfqEiZRmxH4mwW4s8hv4=
=igdK
-----END PGP SIGNATURE-----
Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.
This also unifies the artificial separation of the hclk_vcodec etc clocks
again.
We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.
The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.
On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.
To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.
The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.
Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0
Tested on radxarock-lite.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
mmc sample shift is 0 for rk3228 refer to user manaul.
So it's broken if we enable mmc tuning for rk3228.
Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.
Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Cc: stable@vger.kernel.org # 4.1.x-
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Set clock id for sclk_tsadc gating clock of tsadc in rk3066
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.
So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.
Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.
And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.
Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.
Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
HCLK_VIO_BUS is the noc bus controller clock for display module,
due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference to the Rockchip RK3368 TRM v1.1, some clock
gates need to be updated.
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There is only support rmii in the RK3036, so we should use the correct
ext clock name as described in the TRM.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[update dt-binding document as well]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Due to reference to old version TRM, there are incorrect emac clock node.
The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the
child div.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
To model the muxes downstream of fractional dividers we introduced the
child property, allowing to describe a direct child clock.
The first implementation seems to cause section warnings, as the core
clock-tree is marked as initdata while the data pointed to from the
child element is not.
While there may be some way to also set that missing property in the
inline notation I didn't find it, so to actually fix the issue for now
move the sub-definitions into separate declarations that can have
their own __initdata properties.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288
SoCs only feed those clocks, allow those clocks to change their parents
all the way up the hierarchy.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported Rockchip SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature"
that requires the downstream mux to actually point to the fractional
divider and the fractional divider gate to be enabled, for it to really
accept changes to the divider ratio.
The downstream muxes themselfs are not generic enough to include them
directly into the fractional divider, as they have varying sources of
parent clocks including not only clocks related to the fractional
dividers but other clocks as well.
To solve this, allow our clock branches to specify direct child clock-
branches in the new child property, let the fractional divider register
its downstream mux through this and add a clock notifier that temporarily
switches the mux setting when it notices rate changes to the fractional
divider.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.
The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.
Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.
This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.
For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.
With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.
Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
ACLK_VIO is the noc bus clock for display module, display cann't
read data from ddr without this clock enabled.
Due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference the newly added efuse clock-ids in the clock-tree.
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3228 SoC.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3228's armclk has 3 parents, so allow cpuclk to have
more than 2 parents.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.
Reported-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add aclk_bus and aclk_peri to the list of rk3368 critical clocks,
which are the base clocks that supply for all peripherals, never
to be disabled automatically.
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Most rk3368 boards (especially those with Pmic that followed the lead
from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic.
This is the main voltage for all kinds of misc stuff including the
memory controller.
On these boards it is critically important to make sure that the PWM
never ever glitches and never loses its clock. Any glitch could
crash the system.
Right now there are no users of the PWM regulator and also Linux
thinks that the PWM regulator is disabled. Things happen to work
because firmware configured the PWM and Linux doesn't touch it.
..and the PWM's clock is marked as "ignore unused".
...but things _stop_ working if we turn off serial console. Why?
Because:
1. Serial console shares a parent clock with the PWM (pclk_cpu)
2. If we have no serial console then nobody is holding pclk_cpu on
at reboot time. It gets disabled.
We need to fix a lot of the above problems, but until we get
everything right the cleanest "hack" seems like it is to just keep
the "rk_pwm" clock on always.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Set the newly added id for the crypto clk, so that it can be called
in other parts.
Signed-off-by: Zain Wang <zain.wang@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
