154 Commits

Author	SHA1	Message	Date
Andi Kleen	de4218634e	x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs ... According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>	2008-01-30 13:32:37 +01:00
Simon Arlott	27b46d7661	spelling fixes: arch/i386/ ... Spelling fixes in arch/i386/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Adrian Bunk <bunk@kernel.org>	2007-10-20 01:13:56 +02:00
Thomas Gleixner	c1e3619edd	x86: print info about late C1E detection on 32bit as well ... Some BIOSes set the C1E flag only on the second core. Print a warning so the Firmware Toolkit can check for it. mingo: fix C1E build bug on 32-bit Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>	2007-10-17 20:16:50 +02:00
Thomas Gleixner	f7627e2513	i386: move kernel/cpu ... Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>	2007-10-11 11:16:58 +02:00