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The MPC8548 has 48 internal interrupts and 12 external interrupts. The
previous generation PowerQUICC III devices only had 32 internal and 12
external interrupts on the primary interrupt controller.
Expanded the number of internal interrupts to 48 for all PowerQUICC III
processors and moved the interrupt numbers for the external after the 48
internal interrupt lines, rather than putting the 12 new internal
interrupts at the end and ifdef'ng the whole mess. As parted of this
created a macro which represents the internal interrupt senses since they
are the same on all PQ3 processors.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Adds support for using the MPC8548 processor on the CDS reference board.
Currently all the major busses (PCI, PCI-X, PCI-Express, sRIO) and eTSEC3
and eTSEC4 are not supported.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Added descriptions of the new MPC8548 family processors, e500 core and
peripherals.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
