33 Commits

Author SHA1 Message Date
Conor Dooley
df403b7c95
riscv: dts: icicle: sort nodes alphabetically
The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220509142610.128590-11-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:28:51 -07:00
Conor Dooley
1bcea0303f
riscv: microchip: icicle: readability fixes
Fix the sort order of the status properties, remove some
extra whitespace in the mmc entry & add whitespace to the mac entry
containing the phys so that the dt is easier to read.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220509142610.128590-10-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:28:40 -07:00
Conor Dooley
bc47b2217f
riscv: dts: microchip: add the sundance polarberry
Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-9-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:28:29 -07:00
Conor Dooley
1277b19506
riscv: dts: microchip: make the fabric dtsi board specific
Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
currently since there is only one board with this SoC upstream.

However if another board was added, it would include the fabric contents
of the Icicle Kit's reference design. To avoid this, rename
mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
rather than mpfs.dtsi.

mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference
design for the icicle kit's FPGA fabric & an older version of the
design may not have the i2c or pwm devices - so add the compatible
string to document this.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-6-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:28:11 -07:00
Conor Dooley
da305fa8a9
riscv: dts: microchip: remove soc vendor from filenames
Having the SoC vendor both as the directory and in the filename adds
little. Remove microchip from the filenames so that the files will
resemble the other directories in riscv (and arm64). The new names
follow a soc-board.dts & soc{,-fabric}.dtsi pattern.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-4-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:27:54 -07:00
Conor Dooley
9499e76de5
riscv: dts: microchip: move sysctrlr out of soc bus
The MPFS system controller has no registers of its own, so move it out
of the soc node to avoid dtbs_check warnings:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Suggested-by: Rob Herring <robh@kernel.org>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-3-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:27:48 -07:00
Conor Dooley
8422d1110a
riscv: dts: microchip: remove icicle memory clocks
The clock properties in the icicle kit's memory entries cause dtbs_check
errors:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+'

Get rid of the clocks to avoid the errors.

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220509142610.128590-2-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-06-01 15:27:42 -07:00
Linus Torvalds
265f34c25b RISC-V Fixes for 5.18
* A fix for the fu540-c000 device tree to avoid a schema check failure
   on the DMA node name.
 * A fix to the PolarFire SOC device tree for a typo.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAmKHsFQTHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQRUeD/9NsN9LzFlRKMVCWGcx+ek5lH0Paw7y
 12NFVUa06u1VlBwzrKfWgRN3OzHT8Kt3kTcn82RV7KUpzG5S9OZy9rSv+c4o9wR3
 EtQw4JcSd4X4gIBtVhwqefLPcoufXK1rezH9rcYG7o1cQsd0Lhu81yQxXUf9fFvC
 glOweeE/A5WrYo1NA/FXW/HZVcgjt0QEMhwRDhy0UZFcr6yKc3hE+OBPOTx2dILN
 1bMbTAWBILFnjA2HMFe2xrC+wqMXBNIO8DCAb5cig5IdIAfsRTI4IjcmtYJHOXQO
 APJ20vS83gx2+xznP3fYC4sum1bS5ewAaO3rtERpiaFsY2XVv0nHFxM0/ZTRil/c
 ug+dwI+hzFHPAQ+MtNMbMcNXJO8je5VBODb/MLJiPeir3582eoc5Ov1N6E1zF2wM
 ryCWh8s7OSgfTPYn89SsRRW0Pb8Smq81MIKD0KsnYaxAyQPQagd2aDgMO46pB59O
 KI75ztHbdI5eDJhJZnC+K8oZ3GbUULYNhkx0KzGEDtV52H+JknEsWmeb0Qf2uPFs
 sEjGGrDnCYpze50GARIIJQ0m04DgVsmuUmLwabwxvnCGkWD0tf1jruhAndONDNjl
 KDexMirtpw7e7qgMly9HXigwDcpHXb4zCz3Q7VMvORFymUTyxCcdcMTJOvICZHCv
 OX3S2/h72HnQmQ==
 =hRBq
 -----END PGP SIGNATURE-----

Merge tag 'riscv-for-linus-5.18-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - fix the fu540-c000 device tree to avoid a schema check failure on the
   DMA node name

 - fix typo in the PolarFire SOC device tree

* tag 'riscv-for-linus-5.18-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: dts: microchip: fix gpio1 reg property typo
  riscv: dts: sifive: fu540-c000: align dma node name with dtschema
2022-05-20 08:13:32 -10:00
Conor Paxton
c932edeaf6
riscv: dts: microchip: fix gpio1 reg property typo
Fix reg address typo in the gpio1 stanza.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Link: https://lore.kernel.org/r/20220517104058.2004734-1-conor.paxton@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-05-19 16:47:29 -07:00
Conor Dooley
6deb9bf458 riscv: dts: microchip: reparent mpfs clocks
The 600M clock in the fabric is not the real reference, replace it with
a 125M clock which is the correct value for the icicle kit. Rename the
msspllclk node to mssrefclk since this is now the input to, not the
output of, the msspll clock. Control of the msspll clock has been moved
into the clock configurator, so add the register range for it to the clk
configurator. Finally, add a new output of the clock config block which
will provide the 1M reference clock for the MTIMER and the rtc.

Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-10-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-22 18:40:30 -07:00
Conor Dooley
2b6190c804 riscv: dts: microchip: fix usage of fic clocks on mpfs
The fic clocks passed to the pcie controller and other peripherals in
the device tree are not the clocks they actually run on. The fics are
actually clock domain crossers & the clock config blocks output is the
mss/cpu side input to the interconnect. The peripherals are actually
clocked by fixed frequency clocks embedded in the fpga fabric.

Fix the device tree so that these peripherals use the correct clocks.
The fabric side FIC0 & FIC1 inputs both use the same 125 MHz, so only
one clock is created for them.

Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-4-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-22 18:40:07 -07:00
Conor Dooley
528a5b1f25
riscv: dts: microchip: add new peripherals to icicle kit device tree
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:

2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09 21:46:40 -08:00
Conor Dooley
5b28df37d3
riscv: dts: microchip: update peripherals in icicle kit device tree
Assorted minor changes to the MPFS/Icicle kit device tree:

- enable mmuart4 instead of mmuart0
- remove sifive pdma
- split memory node to match updated fpga design
- move stdout path to serial1 to avoid collision with
        bootloader running on the e51

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09 21:46:40 -08:00
Conor Dooley
c5094f3710
riscv: dts: microchip: refactor icicle kit device tree
Assorted minor changes to the MPFS/Icicle kit device tree:

- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09 21:46:40 -08:00
Conor Dooley
72560c6559
riscv: dts: microchip: add fpga fabric section to icicle kit
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09 21:46:40 -08:00
Conor Dooley
6546f92086
riscv: dts: microchip: use clk defines for icicle kit
Update the Microchip Icicle kit device tree by replacing clock
related magic numbers with their defined counterparts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-03-09 21:46:39 -08:00
Geert Uytterhoeven
e35b07a7df
riscv: dts: microchip: mpfs: Group tuples in interrupt properties
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.

Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09 10:11:28 -08:00
Geert Uytterhoeven
9e85020ccf
riscv: dts: microchip: mpfs: Fix clock controller node
Fix the device node for the clock controller:
  - Remove bogus "reg-names" property,
  - Remove unneeded "clock-output-names" property.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09 10:11:22 -08:00
Geert Uytterhoeven
9d7b307862
riscv: dts: microchip: mpfs: Fix reference clock node
"make dtbs_check" reports:

    arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
	From schema: dtschema/schemas/simple-bus.yaml

Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not
set until bitstream programming time.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09 10:11:17 -08:00
Geert Uytterhoeven
53abf98005
riscv: dts: microchip: mpfs: Fix PLIC node
Fix the device node for the Platform-Level Interrupt Controller (PLIC):
  - Add missing "#address-cells" property,
  - Sort properties according to DT bindings.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09 10:11:11 -08:00
Geert Uytterhoeven
53ef07326a
riscv: dts: microchip: mpfs: Drop empty chosen node
It does not make sense to have an (empty) chosen node in an SoC-specific
.dtsi, as chosen is meant for system-specific configuration.
It is already provided in microchip-mpfs-icicle-kit.dts anyway.

Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-09 10:11:05 -08:00
Palmer Dabbelt
241527bb84 RISC-V DTS changes for v5.16
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
 few minor fixes to make DTSes pass the dtschema, without actual
 functional effect.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmFxLQwQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1/UGD/4vFvmJdbVPd2tDu81qBwrBx13NrAGj2jlM
 6+ZfOzxCZEFd0e+uvhL39f0rm9G7E/TIHtsAc0vL9+InoyByy1UjkCtgDgBAzqPq
 LNmL/QqRsWYivIs7kytnl2Q0b4GS4qflJ9YBe7KHr0apoTFYwIF9pAOCnllG5XG4
 0N94CK/ucWJgkE8R11Zt0cVLBp3ZDJ+rRc9Afqhw/kTznzdVNxjL7h0a1J0FlfH2
 vFDzP34YdUJt5k0eWeu1ZFBpcN5u45/zE/TtiI8hqsehy2+opuiWocKv2duoJZ2F
 X48+Jtw3dahq7KbZPVOnxx/nbEDn4/Bsj/B8Mrqv+wk5BQMRl7L0x2LpbFNJoAB2
 TDsTr19dvCi09C6eA8aVM/FSLeeuexeeJ9U4luthHZWHjEgA94lGSkCHyBlKZGzG
 ro7y25q0lDNBdhxnYZK5PHRJ7sVnSRbMz27cCVQuG6zlSlC8miwNxvTDdscQS5OS
 9sylhsSjvSlkOUNZ9t2SgjcBgX55Qap+TvTIjaOL3rFwwbOzEPPw71pI2OYWy8XD
 piE3wc8zZwUuMHa1BjsE9o0Jy3X3vGJyrY76tId93S7JVOpZB/xsEhtm7SRXOcHm
 kmM1pDOC6OvY+JRhFEohSVBszLhxH2Qm+v7A8z0Ijt1Ellz6kljKYwQLaSp6KCOK
 DvRlr/SstQ==
 =4+vY
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmFxhioTHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRAuExnzX7sYiZgCD/9x9h4aaki1atNgNNW+n+ZACn3pBuBO
 r2mSoUzx1Zvfex2CHQq/2jZce7p+gtVaFuroD3QgySyRcf3FUZwF4Crmg6DotQKO
 TuAzLPCUZAd2HjgvpsgCY8HLzFu7ZRPLtwzph/UaQ6fIVKLF1hbyg/3LMkG7wxUR
 Rxh7h7NTAELlmQjc2SvTRGEX8DyB1HGRereJbNb8DjXjS2+Iezyt5VePwiEME5Z0
 Bmaq1jhBBcmI7IYPxhIn4CDmOY3Xo34ArITwPuOD0eb/kppVal5Tym761aXHnCNZ
 r2/k/p/lXLa5W4nDEDuldM8HwR/KvUgquEYraqw6f1/4u0XRuuk3jifWSHRWkxNj
 QsxyqTqsl44AnNe5vTf2QiuDbGk0Y3C79wmlC4lakcxohUjjwu3EHOdYypyu52W5
 1u4kkVQxVkKCLoJO6/ZBw/BsOk51tXffcHd9SwtKfj1QzJa3JBYgSwDigq37cNQo
 fsv1k0mrZFDWk1fYSGwvzrwSkF4qckLjp0aiSc/0x5YpvZqUNiLpXsWj1eRx/OfM
 rHgVtkfBhsY2ddOflNkXnYlyFRH4twIAknD3dLoDhotvRYMceU28Y2zRjbJGIWFt
 SOXKhDfZRiPYmyMeMh9wUZK4yrdpcSdb8MbTr14UeDhSn8ZnKXberfs4DaXMEsu7
 x90g5jAP8NJ3ag==
 =8DbL
 -----END PGP SIGNATURE-----

Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next

RISC-V DTS changes for v5.16

Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
few minor fixes to make DTSes pass the dtschema, without actual
functional effect.

* tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  riscv: dts: sifive: add missing compatible for plic
  riscv: dts: microchip: add missing compatibles for clint and plic
  riscv: dts: sifive: drop duplicated nodes and properties in sifive
  riscv: dts: sifive: fix Unleashed board compatible
  riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
2021-10-21 08:22:37 -07:00
Krzysztof Kozlowski
73d3c44115 riscv: dts: microchip: add missing compatibles for clint and plic
The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
also Core Local Interruptor and Platform-Level Interrupt Controller are
coming from SiFive.  Add proper compatibles to silence dtbs_check
warnings:

  clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
  interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20210920130412.145231-1-krzysztof.kozlowski@canonical.com
2021-10-19 10:59:57 +02:00
Krzysztof Kozlowski
9406369ae6
riscv: dts: microchip: use vendor compatible for Cadence SD4HC
Licensed IP blocks should have their own vendor compatible.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-10-07 18:33:59 -07:00
Krzysztof Kozlowski
33f736366b
riscv: dts: microchip: drop unused pinctrl-names
pinctrl-names without pinctrl-0 does not have any sense:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: sdhc@20008000: 'pinctrl-0' is a dependency of 'pinctrl-names'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-10-07 18:33:53 -07:00
Krzysztof Kozlowski
42a57a47bb
riscv: dts: microchip: drop duplicated MMC/SDHC node
Devicetree source is a description of hardware and hardware has only one
block @20008000 which can be configured either as eMMC or SDHC.  Having
two node for different modes is an obscure, unusual and confusing way to
configure it.  Instead the board file is supposed to customize the block
to its needs, e.g. to SDHC mode.

This fixes dtbs_check warning:
  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: sdhc@20008000: $nodename:0: 'sdhc@20008000' does not match '^mmc(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-10-07 18:33:48 -07:00
Krzysztof Kozlowski
fd86dd2a5d
riscv: dts: microchip: fix board compatible
According to bindings, the compatible must include microchip,mpfs.  This
fixes dtbs_check warning:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: /: compatible: ['microchip,mpfs-icicle-kit'] is too short

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-10-07 18:33:44 -07:00
Krzysztof Kozlowski
80a9609c93
riscv: dts: microchip: drop duplicated nodes
The DTSI file defines soc node and address/size cells, so there is no
point in duplicating it in DTS file.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-10-07 18:33:38 -07:00
Geert Uytterhoeven
cbba178708
riscv: dts: microchip: mpfs-icicle: Fix serial console
Currently, nothing is output on the serial console, unless
"console=ttyS0,115200n8" or "earlycon" are appended to the kernel
command line.  Enable automatic console selection using
chosen/stdout-path by adding a proper alias, and configure the expected
serial rate.

While at it, add aliases for the other three serial ports, which are
provided on the same micro-USB connector as the first one.

Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-09-10 23:58:19 -07:00
Bin Meng
417166ddec
riscv: dts: microchip: Add ethernet0 to the aliases node
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.

Note on the Icicle Kit board, currently only emac1 is enabled so it
becomes the 'ethernet0'.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-24 20:57:32 -07:00
Bin Meng
719588dee2
riscv: dts: microchip: Use 'local-mac-address' for emac1
Per the DT spec, 'local-mac-address' is used to specify MAC address
that was assigned to the network device, while 'mac-address' is used
to specify the MAC address that was last used by the boot program,
and shall be used only if the value differs from 'local-mac-address'
property value.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: conor dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-08-24 20:56:47 -07:00
Alexandre Ghiti
0ddd7eaffa
riscv: Fix BUILTIN_DTB for sifive and microchip soc
Fix BUILTIN_DTB config which resulted in a dtb that was actually not
built into the Linux image: in the same manner as Canaan soc does,
create an object file from the dtb file that will get linked into the
Linux image.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-06-11 21:07:09 -07:00
Atish Patra
0fa6107eca
RISC-V: Initial DTS for Microchip ICICLE board
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.

https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-04-26 08:31:31 -07:00