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This involves two changes to the BSP code:
1) register_smp_ops() for BMIPS SMP
2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with
the special interrupt vector (IV). Move it to 0x8000_0380 at boot time,
to resolve the conflict.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
[jogo@openwrt.org: moved SMP ops registration into ifdef guard,
changed ifdef guards to if (IS_ENABLED())]
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/5489/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Broadcom BCM3368 Cable Modem SoC is extremely similar to the
existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort
in the existing code base is required to get it supported. This patch adds
support for the following on-chip peripherals:
- two UARTS
- GPIO
- Ethernet
- SPI
- PCI
- NOR Flash
The most noticeable difference with 3368 is that it has its peripheral
register at 0xfff8_0000 we check that separately in ioremap.h. Since
3368 is identical to 6358 for its clock and reset bits, we use them
verbatim.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI)
on BMIPS SMP. Make the board support code aware of them.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
[jogo@openwrt.org: move sw irqs behind timer irq]
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/5354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Remove the bogus selects on USB-related symbols for 6345 and 6338, not
only we do not yet support USB on BCM63XX, but they also cause the
following warnings:
warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects
USB_OHCI_BIG_ENDIAN_MMIO which has unmet direct dependencies
(USB_SUPPORT && USB && USB_OHCI_HCD)
warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects
USB_OHCI_BIG_ENDIAN_DESC which has unmet direct dependencies
(USB_SUPPORT && USB && USB_OHCI_HCD)
make[4]: Leaving directory `/home/florian/dev/linux'
Just get rid of these bogus Kconfig selects because neither 6345 nor
6338 actually have built-in USB host controllers.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: http://patchwork.linux-mips.org/patch/5497/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
has a slightly different and older DMA engine which requires the
following modifications:
- the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
which means that the helpers enet_dma{c,s} need to account for this
channel width and we can no longer use macros
- BCM6345 DMA engine does not have any internal SRAM for transfering
buffers
- BCM6345 buffer allocation and flow control is not per-channel but
global (done in RSET_ENETDMA)
- the DMA engine bits are right-shifted by 3 compared to other DMA
generations
- the DMA enable/interrupt masks are a little different (we need to
enabled more bits for 6345)
- some register have the same meaning but are offsetted in the ENET_DMAC
space so a lookup table is required to return the proper offset
The MAC itself is identical and requires no modifications to work.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
which needs to be driven slightly differently from the traditional
external switches. This patch introduces changes in arch/mips/bcm63xx in order
to:
- register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
- update DMA channels configuration & state RAM base addresses
- add a new platform data configuration knob to define the number of
ports per switch/device and force link on some ports
- define the required switch registers
On the driver side, the following changes are required:
- the switch ports need to be polled to ensure the link is up and
running and RX/TX can properly work
- basic switch configuration needs to be performed for the switch to
forward packets to the CPU
- update the MIB counters since the integrated
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
The current bcm63xx_enet driver always uses bcmenet_shared_base whenever
it needs to access DMA channel configuration space or access the DMA
channel state RAM. Split these register in 3 parts to be more accurate:
- global DMA configuration
- per DMA channel configuration space
- per DMA channel state RAM space
This is preliminary to support new chips where the global DMA
configuration remains the same, but there is a varying number of DMA
channels located at a different memory offset.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull MIPS updates from Ralf Baechle:
- More work on DT support for various platforms
- Various fixes that were to late to make it straight into 3.9
- Improved platform support, in particular the Netlogic XLR and
BCM63xx, and the SEAD3 and Malta eval boards.
- Support for several Ralink SOC families.
- Complete support for the microMIPS ASE which basically reencodes the
existing MIPS32/MIPS64 ISA to use non-constant size instructions.
- Some fallout from LTO work which remove old cruft and will generally
make the MIPS kernel easier to maintain and resistant to compiler
optimization, even in absence of LTO.
- KVM support. While MIPS has announced hardware virtualization
extensions this KVM extension uses trap and emulate mode for
virtualization of MIPS32. More KVM work to add support for VZ
hardware virtualizaiton extensions and MIPS64 will probably already
be merged for 3.11.
Most of this has been sitting in -next for a long time. All defconfigs
have been build or run time tested except three for which fixes are being
sent by other maintainers.
Semantic conflict with kvm updates done as per Ralf
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (118 commits)
MIPS: Add new GIC clockevent driver.
MIPS: Formatting clean-ups for clocksources.
MIPS: Refactor GIC clocksource code.
MIPS: Move 'gic_frequency' to common location.
MIPS: Move 'gic_present' to common location.
MIPS: MIPS16e: Add unaligned access support.
MIPS: MIPS16e: Support handling of delay slots.
MIPS: MIPS16e: Add instruction formats.
MIPS: microMIPS: Optimise 'strnlen' core library function.
MIPS: microMIPS: Optimise 'strlen' core library function.
MIPS: microMIPS: Optimise 'strncpy' core library function.
MIPS: microMIPS: Optimise 'memset' core library function.
MIPS: microMIPS: Add configuration option for microMIPS kernel.
MIPS: microMIPS: Disable LL/SC and fix linker bug.
MIPS: microMIPS: Add vdso support.
MIPS: microMIPS: Add unaligned access support.
MIPS: microMIPS: Support handling of delay slots.
MIPS: microMIPS: Add support for exception handling.
MIPS: microMIPS: Floating point support.
MIPS: microMIPS: Fix macro naming in micro-assembler.
...
Instead of trying to use a correlation of cpu prid and chip id and
hoping they will always be unique, use the cpu prid to determine the
chip id register location and just read out the chip id.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5008/
Acked-by: John Crispin <blogic@openwrt.org>
BCM6338 and BCM6348, and BCM6358 and everything after that share the
same register layout. To not have to redefine them for each new chip
and keep the code size small, only use the definitions for the first
chip with the certain layout.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5006/
Acked-by: John Crispin <blogic@openwrt.org>
Pull spi updates from Mark Brown:
"A fairly quiet release for SPI, mainly driver work. A few highlights:
- Supports bits per word compatibility checking in the core.
- Allow use of the IP used in Freescale SPI controllers outside
Freescale SoCs.
- DMA support for the Atmel SPI driver.
- New drivers for the BCM2835 and Tegra114"
* tag 'spi-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (68 commits)
spi-topcliff-pch: fix to use list_for_each_entry_safe() when delete list items
spi-topcliff-pch: missing platform_driver_unregister() on error in pch_spi_init()
ARM: dts: add pinctrl property for spi node for atmel SoC
ARM: dts: add spi nodes for the atmel boards
ARM: dts: add spi nodes for atmel SoC
ARM: at91: add clocks for spi dt entries
spi/spi-atmel: add dmaengine support
spi/spi-atmel: add flag to controller data for lock operations
spi/spi-atmel: add physical base address
spi/sirf: fix MODULE_DEVICE_TABLE
MAINTAINERS: Add git repository and update my address
spi/s3c64xx: Check for errors in dmaengine prepare_transfer()
spi/s3c64xx: Fix non-dmaengine usage
spi: omap2-mcspi: fix error return code in omap2_mcspi_probe()
spi/s3c64xx: let device core setup the default pin configuration
MAINTAINERS: Update Grant's email address and maintainership
spi: omap2-mcspi: Fix transfers if DMADEVICES is not set
spi: s3c64xx: move to generic dmaengine API
spi-gpio: init CS before spi_bitbang_setup()
spi: spi-mpc512x-psc: let transmiter/receiver enabled when in xfer loop
...
speed_hz is a write only member, so we can safely remove it and its
generation. Also fixes the missing clk_put after getting the periph
clock.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit causes a race between PCI scan and SSB fallback SPROM handler
registration, causing the wifi to not work on slower systems. The only
subsystem touched from board_register_devices is platform device
registration, which is safe as an arch init call.
This reverts commit d64ed7ada2 [MIPS:
BCM63XX: Call board_register_device from device_initcall()].
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
To: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We cannot use __init for earlyprintk code or data, since the kernel
parameter "keep_bootcon" allows leaving the boot console enabled.
Currently MIPS will crash/hang/die if you use keep_bootcon. The patch
fixes it at least on Lemote FuLoong mini-PC. Changes for other boards
were done based on what I could find with grep...
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Patchwork: http://patchwork.linux-mips.org/patch/4935/
Signed-off-by: John Crispin <blogic@openwrt.org>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The current checksum calculation code does nothing except checking that
the first byte of nvram is 0 without actually checking the checksum.
Implement the correct checksum calculation by calculating the crc32 with
the checksum field set to 0.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4540
Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
...
While calculating the mac address the pointer for the current octet was
never reset back to the least significant one after being decremented
because of an octet overflow. This resulted in the code continuing to
increment at the current octet, potentially generating duplicate or
invalid mac addresses.
As a second issue the pointer was allowed to advance up to the most
significant octet, modifying the OUI, and potentially changing the type
of mac address.
Rewrite the code so it resets the pointer to the least significant
in each outer loop step, and bails out when the least significant octet
of the OUI is reached.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
Patchwork: https://patchwork.linux-mips.org/patch/4348/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
BCM6338 and BCM6348 have a message control register width of 8 bits, instead
of 16-bits like what the SPI driver assumes right now. Also the SPI message
type shift value of 14 is actually 6 for these SoCs.
This resulted in transmit FIFO corruption because we were writing 16-bits
to an 8-bits wide register, thus spanning on the first byte of the transmit
FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
Fix this by passing the message control register width and message type
shift through platform data back to the SPI driver so that it can use
it properly.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Cc: jonas.gorski@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/3983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
