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Add support for 25G devices - defines and data structures.
One tricky part here is that the firmware support for these
Devices introduces a mismatch between the PHY type enum and
the bitfields for the phy types.
This change creates a macro and uses it to increment the 25G
PHY values when creating 25G bitfields.
Change-ID: I69b24d837d44cf9220bf5cb8dd46c5be89ce490b
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This patch fixes byte ordering problems found when enabling this feature
support. Without this patch, the feature will not work correctly. This
patch fixes the definitions to have the correct byte order.
Change-ID: Ic7489fbcbe2195df7be62ff5e359201b827cefe6
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Remove the code that implements the HMC AQ APIs and call these APIs.
This is done because these are obsolete APIs and are not supported
by firmware.
Change-ID: I5d771d8f37c3e16e7b0a972ff9b27e75aa2d05d4
Signed-off-by: Neerav Parikh <neerav.parikh@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Add device capability which defines if update is available and security
check is needed during update process.
Change-ID: I380787c878275e1df18b39198df3ee3666342282
Signed-off-by: Michal Kosiarz <michal.kosiarz@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Add the new opcodes and struct used for asking the firmware to update Rx
control registers that need extra care when being accessed while under
heavy traffic - e.g. sustained 64byte packets at line rate on all ports.
The firmware will take extra steps to be sure the register accesses
are successful.
The registers involved are:
PFQF_CTL_0
PFQF_HENA
PFQF_FDALLOC
PFQF_HREGION
PFLAN_QALLOC
VPQF_CTL
VFQF_HENA
VFQF_HREGION
VSIQF_CTL
VSILAN_QBASE
VSILAN_QTABLE
VSIQF_TCREGION
PFQF_HKEY
VFQF_HKEY
PRTQF_CTL_0
GLFCOE_RCTL
GLFCOE_RSOF
GLQF_CTL
GLQF_SWAP
GLQF_HASH_MSK
GLQF_HASH_INSET
GLQF_HSYM
GLQF_FC_MSK
GLQF_FC_INSET
GLQF_FD_MSK
PRTQF_FD_INSET
PRTQF_FD_FLXINSET
PRTQF_FD_MSK
Change-ID: I56c8144000da66ad99f68948d8a184b2ec2aeb3e
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
In MFP mode particularly when we were setting the PF VSI in limited
promiscuous, the HW switch was still mirroring the outgoing packets
from other VSIs (VF/VMdq) onto the PF VSI.
With this new bit set, the mirroring doesn't happen any more and so
we are in limited promiscuous on the PF VSI in MFP which is similar
to defport.
An API check is not required, since this bit is reserved for FW API
version < 1.5
Also update copyright year in file headers.
Change-ID: I9840cb95f11dde733d943cb03ce84f68b9611bc8
Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Add flags to MAC allocation requests to signify that the MAC VLAN filters
should come from the shared resource pool rather than the dedicated PF
resource pools.
Change-ID: I4c2da64c01856edcb0982bc4aab75c5a91047a7a
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Acked-by: Kevin Scott <kevin.c.scott@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
The device capabilities were defined in two places, and neither had all
the definitions. It really belongs with the AQ API definition, so this
patch removes the other set of definitions and fills out the missing item.
Change-ID: I273ba7d79a476cd11d2e0ca5825fec1716740de2
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Acked-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This is a part of implementation which contains data structures and
opcode for new AQ command. There's a new ARQ message that gets sent
near the end of the NVM update process that the driver should recognize
and ignore, rather than printing an Unknown Event error.
Change-ID: I04830a5bcae14823e16b9424cc4165e169336c1f
Signed-off-by: Michal Kosiarz <michal.kosiarz@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Add the new Port link status bit and rename the link status to function
link status.
Change-ID: I71289327ae62638ce967b6ad40114caf998b6dab
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Add struct size checks to many of the indirect structs and a few
command structs that were left out previously.
Change-ID: I7810b9af0f04e3ced670639f8671daf7df9b3f4d
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Acked-by: Greg Rose <gregory.v.rose@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Several little tweaks to keep FW, SV, and SW in line together
- Remove the unused and deprecated
i40e_aqc_opc_debug_modify_internals
- Add define for iSCSI capability
- Fix queue mask size
- Adjust i40e_aqc_oem_param_change for ease-of-use
Change-ID: I51f250b367912968a7cec61b3a68110d9796e914
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Kamil Kacperski <kamil.kacperski@intel.com>
Acked-by: Greg Rose <gregory.v.rose@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This is one small step in making the indentation more consistent. If
we truly want to align values, then use tabs rather than spaces.
Change-ID: I12368bc77a52f296d1843fdcb67201a7d7cd4749
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Tested-by: Jim Young <jamesx.m.young@intel.com>
Add set_pf_context, replace set_phy_reset with set_phy_debug, add
nvm_config_read/write, remove nvm_read/write_reg_se and add some
PHY types.
With these changes we bump the API version to 1.2.
Change-ID: I4dc3aec175c2316f66fc9b726b3f7d594699d84e
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
