cb26f8925c
drm/amd/display: use different sr latencies for dpm0 dcn bw calc
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:08:10 -04:00
90f095c13e
drm/amd/display: add pipe split disable regkey
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:08:07 -04:00
7f5c22d165
drm/amd/display: RV stereo support
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HDMI frame pack and DP frame alternate in band
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:08:00 -04:00
f0558542a7
drm/amd/display: redesign mpc
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:57 -04:00
c9742685c2
drm/amd/display: add bw logging for dcn
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:56 -04:00
7fa4fcba7a
drm/amd/display: Don't guard x86 in Makefile
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make-kpkg doesn't seem to like it
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:37 -04:00
bf2e2e2e0e
drm/amd/display: Limit DCN to x86 arch
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DCN bw calcs currently rely on the following gcc options:
-mhard-float -msse -mpreferred-stack-boundary=4
We probably shouldn't really try building this on architectures
other than x86.
CC: Alex Deucher <Alexander.Deucher@amd.com >
CC: Christian König <christian.koenig@amd.com >
CC: Michel Dänzer <michel.daenzer@amd.com >
CC: Tony Cheng <Tony.Cheng@amd.com >
CC: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:32 -04:00
ca3cba9c60
drm/amd/display: single channel bandwidth verses dual channel bandwidth
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DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth
for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth
Signed-off-by: Charlene Liu <charlene.liu@amd.com >
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:04 -04:00
d4b4597384
drm/amd/display: Add 64KB_S_T and 64KB_D_T swizzle mode.
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Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:03 -04:00
9037d802a9
drm/amd/display: refactor bw related variable structure in val_ctx
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:07:01 -04:00
64b44524d4
drm/amd/display: bw debug options now apply to dml as well
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:06:55 -04:00
ff5ef99248
drm/amdgpu/display: Enable DCN in DC
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Enable DCN in DC.
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:06:51 -04:00
74c49c7ac1
drm/amdgpu/display: Add calcs code for DCN
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Bandwidth and scaling calculations for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 18:06:47 -04:00
dff06ddd7f
drm/amd/display: fix dce_calc surface pitch setting for non underlay pipes
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:22:03 -04:00
5e141de452
drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h
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Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:21:01 -04:00
faddcb360c
drm/amd/display: fix bw calc internal initialization error
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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:19:57 -04:00
1de8c33bbd
drm/amd/display: Fixed bandwidth calculation error when converting fractions
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[Problem]
VSR greyed out
[Root cause]
When converting fractions, we were using the integer function, which let to
a large display clock and the view was not supported
[Solution]
Change the integer to fraction functions
Signed-off-by: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:19:49 -04:00
8fa9ca2ec6
drm/amd/display: Remove DCE12 guards
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Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com >
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:19:36 -04:00
2c8ad2d5a2
drm/amd/display: Enable DCE12 support
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This wires DCE12 support into DC and enables it.
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:19:23 -04:00
4ef3a67b6a
drm/amd/display: rename bandwidth_calcs.c to dce_calcs.c (v2)
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v2: agd: squash in the Makefile change as well.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Eagle Yeh <eagle.yeh@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:15:47 -04:00
e266fdf694
drm/amd/display: Enable regamma 25 segments and use double buffer.
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Moved custom floating point calculation to the shared place
between dce's.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:14:18 -04:00
ffbcd19a88
drm/amd/display: Adding 10 bpcc video P010 format
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Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:13:40 -04:00
8693049a89
drm/amd/display: rename BGRA8888 to ABGR8888
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DC actually support ABGR8888 instead of BGRA8888 (R/B swap rather than endian swap) ,
rename to avoid confusion
Signed-off-by: Tony Cheng <tony.cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:11:00 -04:00
fcd2f4bf8b
drm/amd/display: Output Transfer Function Regamma Refactor
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- Create translation function to translate logical format to hw format
- Refactor to use transfer function in dc instead of input gamma
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:09:48 -04:00
02dfc70737
drm/amd/display: Add Polaris12 to bw_calc
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Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:09:33 -04:00
00c91d0d48
drm/amd/display: Support 64-bit Polaris11 5k VSR
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- pass full asic_id info into bw_calc_init instead of only version enum
- 64-bit Polaris11 needs an extra microsecond of dmif_urgent_latency
- add helper to convert from asic_id.family to bw_calc version enum
Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:09:20 -04:00
7a8b8b1403
drm/amd/display: Remove unused function in gamma_calcs
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Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:08:33 -04:00
d7194cf6b8
drm/amd/display: Implement gamma correction using input LUT
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The dc_gamma in dc_surface will be programmed to the input
LUT if provided. If dc_gamma is not provided in dc_surface
regamma may be used to emulate gamma.
Some refactor and cleanup included as well.
Signed-off-by: Aric Cyr <aric.cyr@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:06:52 -04:00
6f3f8d4866
drm/amd/display: Fix Regamma end point
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1. HW register programmed to wrong value
2. End slope for PQ case not calculated correctly
Signed-off-by: Anthony Koo <anthony.koo@amd.com >
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:06:27 -04:00
538735e9e5
drm/amd/display: Fix programming of gamma end points
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Signed-off-by: Anthony Koo <anthony.koo@amd.com >
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:05:54 -04:00
4a69244eb6
drm/amd/display: Fix distribution of segments for PQ
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For PQ case, redistribution of segments should be done differently
for FP16 case in order to handle content above FP16 value of 1.0
Signed-off-by: Anthony Koo <anthony.koo@amd.com >
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:05:51 -04:00
e63d86dc9b
drm/amd/display: Implement PQ curve based on output transfer function
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Refactor part 5 - Regamma programming should be dependent on Output
transfer function type
Program sRGB gamma or PQ transfer function based on output transfer
function.
Signed-off-by: Anthony Koo <anthony.koo@amd.com >
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:05:44 -04:00
a33fa99d8b
drm/amd/display: Fix bunch of warnings in DC
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Some of those are potential bugs
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com >
Acked-by: Harry Wentland <Harry.Wentland@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:04:17 -04:00
4562236b3b
drm/amd/dc: Add dc display driver (v2)
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Supported DCE versions: 8.0, 10.0, 11.0, 11.2
v2: rebase against 4.11
Signed-off-by: Harry Wentland <harry.wentland@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-09-26 17:01:32 -04:00