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Raw NAND core changes:
* Add support for manufacturer specific suspend/resume operation
* Add support for manufacturer specific lock/unlock operation
* Replace zero-length array with flexible-array member
* Fix a typo ("manufecturer")
* Ensure nand_soft_waitrdy wait period is enough
Raw NAND controller driver changes:
* Brcmnand:
Add support for flash-edu for dma transfers (+ bindings)
* Cadence:
Reinit completion before executing a new command
Change bad block marker size
Fix the calculation of the avaialble OOB size
Get meta data size from registers
* Qualcom:
Use dma_request_chan() instead dma_request_slave_channel()
Release resources on failure within qcom_nandc_alloc()
* Allwinner:
Use dma_request_chan() instead dma_request_slave_channel()
* Marvell:
Use dma_request_chan() instead dma_request_slave_channel()
Release DMA channel on error
* Freescale:
Use dma_request_chan() instead dma_request_slave_channel()
* Macronix:
Add support for Macronix NAND randomizer (+ bindings)
* Ams-delta:
Rename structures and functions to gpio_nand*
Make the driver custom I/O ready
Drop useless local variable
Support custom driver initialisation
Add module device tables
Handle more GPIO pins as optional
Make read pulses optional
Don't hardcode read/write pulse widths
Push inversion handling to gpiolib
Enable OF partition info support
Drop board specific partition info
Use struct gpio_nand_platdata
Write protect device during probe
* Ingenic:
Use devm_platform_ioremap_resource()
Add dependency on MIPS || COMPILE_TEST
* Denali:
Deassert write protect pin
* ST:
Use dma_request_chan() instead dma_request_slave_channel()
Raw NAND chip driver changes:
* Toshiba:
Support reading the number of bitflips for BENAND (Built-in ECC NAND)
* Macronix:
Add support for deep power down mode
Add support for block protection
SPI-NAND core changes:
* Do not erase the block before writing a bad block marker
* Explicitly use MTD_OPS_RAW to write the bad block marker to OOB
* Stop using spinand->oobbuf for buffering bad block markers
* Rework detect procedure for different READ_ID operation
SPI-NAND driver changes:
* Toshiba:
Support for new Kioxia Serial NAND
Rename function name to change suffix and prefix (8Gbit)
Add comment about Kioxia ID
* Micron:
Add new Micron SPI NAND devices with multiple dies
Add M70A series Micron SPI NAND devices
identify SPI NAND device with Continuous Read mode
Add new Micron SPI NAND devices
Describe the SPI NAND device MT29F2G01ABAGD
Generalize the OOB layout structure and function names
The suffix was changed from "G" to "J" to classify between 1st generation
and 2nd generation serial NAND devices (which now belong to the Kioxia
brand).
As reference that's
1st generation device of 1Gbit product is "TC58CVG0S3HRAIG"
2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ".
The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and
the prefix was changed from "TC58" to "TH58".
Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*().
Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com
Macronix AD series support deep power down mode for a minimum
power consumption state.
Overload nand_suspend() & nand_resume() in Macronix specific code to
support deep power down mode.
Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.
Hence, we disable the feature at probe time.
Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200311175735.2007-5-sshivamurthy@micron.com
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones is a flexible array member[1][2],
introduced in C99:
struct foo {
int stuff;
struct boo array[];
};
By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on.
Also, notice that, dynamic memory allocations won't be affected by
this change:
"Flexible array members have incomplete type, and so the sizeof operator
may not be applied. As a quirk of the original implementation of
zero-length arrays, sizeof evaluates to zero."[1]
This issue was found with the help of Coccinelle.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 7649773293 ("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200226222722.GA18020@embeddedor
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df4652 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.
This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07ee ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.
To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.
Fixes: 7529df4652 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
Macronix NANDs support randomizer operation for user data scrambled,
which can be enabled with a SET_FEATURE.
User data written to the NAND device without randomizer is still readable
after randomizer function enabled.
The penalty of randomizer are subpage accesses prohibited and more time
period is needed in program operation and entering deep power-down mode.
i.e., tPROG 300us to 340us(randomizer enabled)
For more high-reliability concern, if subpage write not available with
hardware ECC and then to enable randomizer is recommended by default.
Driver checks byte 167 of Vendor Blocks in ONFI parameter page table
to see if this high-reliability function is supported. By adding a new
specific DT property in children nodes to enable randomizer function.
Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1581922600-25461-2-git-send-email-masonccyang@mxic.com.tw
In order to be merged with "gpio-nand", the driver must support custom
(non-GPIO) I/O accessors.
Allow platforms to omit data GPIO port as well as NWE pin info from
device setup. For the driver to still work on such platform, custom
I/O accessors as well as a custom probe function which initialises the
driver private structure with those accessors must be added to the
driver.
Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-14-jmkrzyszt@gmail.com
Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
Tested on GD5F1GQ4UAYIG and W25N01GVZEIG.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200208074439.146296-1-gch981213@gmail.com