Commit Graph

7 Commits

Author SHA1 Message Date
Paul Cercueil
fc18139c28 mips: ingenic: Enable EXT/2 divider on JZ4750/55/60 if EXT is 24 MHz
The JZ4750, JZ4755 and JZ4760 (non-B version) support using a 24 MHz
external crystal oscillator instead of the typical 12 MHz one.

However, most of the SoC's IP blocks only work with a 12 MHz clock.
Thanksfully, there is a /2 divider we can enable when a 24 MHz external
crystal is present.

Force-enable this /2 divider when the oscillator is 24 MHz, so that the
SoC always uses a 12 MHz clock internally.

It is done here, and not in the clocks driver, because we need the EXT
clock to be 12 MHz for the early console to work, and the clocks driver
probes way too late.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09 09:54:17 +02:00
Paul Cercueil
50a1171d3b mips: ingenic: Remove useless __maybe_unused
These flags are useless in this case as the code referencing these data
structures is always seen by the compiler (and not behind #ifdef
guards).

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09 09:54:17 +02:00
Aidan MacDonald
2b0f3d70ce mips: ingenic: Do not manually reference the CPU clock
It isn't necessary to manually walk the device tree and enable
the CPU clock anymore. The CPU and other necessary clocks are
now flagged as critical in the clock driver, which accomplishes
the same thing in a more declarative fashion.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220428164454.17908-4-aidanmacdonald.0x0@gmail.com
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18 13:56:26 -07:00
Paul Cercueil
71f8817c28 MIPS: ingenic: Unconditionally enable clock of CPU #0
Make sure that the PLL that feeds the CPU won't be stopped while the
kernel is running.

This fixes a problem on JZ4760 (and probably others) where under very
specific conditions, the main PLL would be turned OFF when the kernel
was shutting down, causing the shutdown process to fail.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-08-29 13:31:02 +02:00
周琰杰 (Zhou Yanjie)
14d72af7ab MIPS: Ingenic: Add system type for new Ingenic SoCs.
Add JZ4730, JZ4750, JZ4755, JZ4760, JZ4760B, X2000H, and X2100 system
type for cat /proc/cpuinfo to give out JZ4730, JZ4750, JZ4755, JZ4760,
JZ4760B, X2000H, and X2100.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-07-19 13:16:42 +02:00
周琰杰 (Zhou Yanjie)
a9fee3a513 MIPS: Ingenic: Add system type for new Ingenic SoCs.
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo
to give out JZ4775, X1000E, X2000 and X2000E.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27 10:57:27 +02:00
Paul Cercueil
f0f4a75307 MIPS: generic: Add support for Ingenic SoCs
Add support for Ingenic SoCs in arch/mips/generic/.

The Kconfig changes are here to ensure that it is possible to compile
either a generic kernel that supports Ingenic SoCs, or a Ingenic-only
kernel, both using the same code base, to avoid duplicated code.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:33:59 +02:00