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The WM8350 core won't actually use the range yet, but it will in
future and the platform data to configure it is there now.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This makes it a bit more obvious in genirq diagnostics that they
aren't handled by the i.MX interrupt controller.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
They will be automatically powered off at startup so users will
need to enable them for use.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
otg_ulpi_create is defined in drivers/usb/otg/ulpi.c which depends on
CONFIG_USB_ULPI. So protect its usage by the same symbol. Moreover
mxc_ulpi_access_ops needs CONFIG_MXC_ULPI.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Valentin Longchamp <valentin.longchamp@epfl.ch>
Cc: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 52939c03 (ARM: MX3: fix CPU revision number detection) started
using the CPU's SREV register for revision number detection. This
makes it mandatory to have a valid SPBA0 mapping. Add this to the
global map_io code instead of adding multiple copies for each board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Tested on Qong (EVB-Lite)
Tested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Check whether L2 is present or not in XSC3. If it's present, enable L2
immediately.
Disabling L2 after L2 is enabled that would result in unpredicatable behavior
of XSC3 processor.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3,
it would enable L2. This operation is evil that would make system hang.
In XSC3 core document, these words are mentioned in below.
"Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2
Cache, software may set the bit to a '1' before or at the same time as enabling
the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the
L2 Cache after the L2 Cache has been enabled, may result in unpredictable
behavior of the processor."
When outer cache is initialized, the MMU is already enabled. We couldn't enable
L2 after MMU enabled.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
PXA mmc host driver supports card detect, read only and power gpio pin
setting already. Zylonite platform driver needn't implement this any more.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
ARRAY_AND_SIZE is already defined arch/arm/mach-mmp/common.h which is
already included.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Bin Yang <bin.yang@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
DM9000s on Zeus sometime fail under heavy load.
Relaxing the timings a bit seems to be of a great help.
Signed-off-by: Marc Zyngier <maz@misterjones.org>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
This has to be selected, otherwise some peripherals don't get initialized.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Use resource_size for {request/release}_mem_region and ioremap.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
The PCIe inbound window size is supposed to be a power of two. If
the total amount of RAM installed in the system is not a power of two,
round it up such that it is.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This fixes a "start_kernel(): bug: interrupts were enabled early".
rtc_cmos now takes care of initializing the ISA RTC and reading the
current time and date from it; there's no need to repeat that here,
thereby causing interrupts to be enabled too early.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PAGE_KERNEL should not be executable; any area marked executable can
be prefetched into the instruction cache. We don't want vmalloc areas
to be read in this way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix two bugs in s3c_nand_set_platdata() where thet device's platform
data was not set, and the wrong error check was being performed on
the return of s3c_nand_copy_set().
Fixes the following OOPS:
Unable to handle kernel NULL pointer dereference at virtual address 00000004
PC is at s3c24xx_nand_probe+0x234/0x594
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
It is unpredictable to have the same memory mapped using different
shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU
write buffer bug test.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add definition for the touchscreen driver platform data and initial
support for the H1940 machine.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add the NAND_SCAN_SILENT_NODEV to the optional NAND devices that may not
be fitted to the board
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Simtec Linux Team <linux@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Add the NAND_SCAN_SILENT_NODEV to the optional NAND devices that may not
be fitted to the board
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Simtec Linux Team <linux@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Commit f74f7e57ae9fa12b2951ae62ce3557799b318399 (ARM: use
flush_kernel_dcache_area() for dmabounce) has broken dmabounce build:
CC arch/arm/common/dmabounce.o
arch/arm/common/dmabounce.c: In function 'unmap_single':
arch/arm/common/dmabounce.c:315: error: implicit declaration of function '__cpuc_flush_kernel_dcache_area'
make[2]: *** [arch/arm/common/dmabounce.o] Error 1
Fix it.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix bug of uart0 platfrom data for nuc900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
putc support for nuc900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
fix compiling error for NUC900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On Oprofile ARMv7 the PMNC_D bit was set to lower the PMU IRQs
and so to decrease the risk of errata #628216 from appearing.
The effect of setting the PMNC_D bit is that the CCNT counter
is divided by 64, making the program counter events count
inaccurate.
The new OMAP3 r4 cores should have that errata fixed.
The PMNC_D bit should not be set, this patch fixes it.
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
26-bit ARM support was removed a long time ago, and this symbol has
been defined to be 'y' ever since. As it's never disabled anymore,
we can kill it without any side effects.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This avoids races in the VFP code where the dead thread may have
state on another CPU. By moving this code to exit_thread(), we
will be running as the thread, and therefore be running on the
current CPU.
This means that we can ensure that the only local state is accessed
in the thread notifiers.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 2c9b9c849 added an argument to __cpuc_flush_dcache_page
and renamed it.
Update a caller of the old function to fix this build error:
CC arch/arm/mm/copypage-v6.o
arch/arm/mm/copypage-v6.c: In function 'v6_copy_user_highpage_nonaliasing':
arch/arm/mm/copypage-v6.c:51: error: implicit declaration of function '__cpuc_flush_dcache_page'
make[1]: *** [arch/arm/mm/copypage-v6.o] Error 1
make: *** [arch/arm/mm] Error 2
Reported-by: Jinsung Yang <jsgood.yang@samsung.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
OMAP3: serial - fix bug introduced in
mfd: twl: fix twl4030 rename for remaining driver, board files
USB ehci: replace mach header with plat
omap3: Allow EHCI to be built on OMAP3
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6:
spi: spi_txx9.c: use resource_size()
spi: spi_sh_sci.c: use resource_size()
spi: spi_mpc8xxx.c: use resource_size()
spi: spi_bfin5xx.c: use resource_size()
spi: atmel_spi.c: use resource_size()
spi: Add s3c64xx SPI Controller driver
atmel_spi: fix dma addr calculation for len > BUFFER_SIZE
spi_s3c24xx: add FIQ pseudo-DMA support
spi: controller driver for Designware SPI core
spidev: add proper section markers
spidev: use DECLARE_BITMAP instead of declaring the array
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
PCMCIA: fix pxa2xx_lubbock modular build error
[ARM] Update mach-types
[ARM] pxa: fix no reference of cpu_is_pxa25x() in devices.c
[ARM] pxa/cm-x300: add PWM backlight support
revert "[ARM] pxa/cm-x300: add PWM backlight support"
ARM: use flush_kernel_dcache_area() for dmabounce
ARM: add size argument to __cpuc_flush_dcache_page
ARM: 5848/1: kill flush_ioremap_region()
ARM: cache-l2x0: make better use of background cache handling
ARM: cache-l2x0: avoid taking spinlock for every iteration
[ARM] Kirkwood: Add LaCie Network Space v2 support
ARM: dove: fix the mm mmu flags of the pj4 procinfo
Add pseudo-DMA by FIQ to the S3C24XX SPI driver. This allows the driver
to get DMA-like performance where there are either no free DMA channels or
when doing transfers that required both TX and RX data paths.
Since this patch requires the addition of an assembly file to hold the FIQ
code, we rename the module (instead of adding a rename of the .c file to
this patch). We expect most users are loading this via udev and thus
there should be no change to the userland configuration.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Simtec Linux Team <linux@simtec.co.uk>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
