3 Commits

Author	SHA1	Message	Date
Sascha Hauer	2b254693be	ARM i.MX6: remove gate_mask from pllv3 ... Now that the additional enable bits in the enet PLL are handled as gates, the gate_mask is identical for all plls. Remove the gate_mask from the code and use the BM_PLL_ENABLE bit for enabling/disabling the PLL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>	2012-11-22 15:32:39 +01:00
Sascha Hauer	7a04092c73	ARM i.MX6: Fix ethernet PLL clocks ... In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz and has different outputs. Only the enet reference clock is implemented. This patch changes the PLL so that it outputs 500MHz and adds the additional outputs as dividers. This now matches the datasheet which says: > This PLL synthesizes a low jitter clock from 24 MHz reference clock. > The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are: > • Ref_PCIe = 125 MHz > • Ref_SATA = 100 MHz > • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>	2012-11-22 15:32:33 +01:00
Shawn Guo	a3f6b9dbf2	ARM: imx: add common clock support for pllv3 ... This PLL is found on i.MX6 SoCs Signed-off-by: Shawn Guo <shawn.guo@linaro.org>	2012-05-02 12:08:06 +02:00