2 Commits

Author	SHA1	Message	Date
Emil Renner Berthing	3d70b9853b	dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible ... This cache controller is also used on the StarFive JH7100 SoC. Unfortunately it needs a quirk to work properly, so add dedicated compatible string to be able to match it. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>	2023-11-22 11:58:08 +00:00
Conor Dooley	dc8ea9204b	dt-bindings: move cache controller bindings to a cache directory ... There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>	2023-04-04 12:12:13 -05:00