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Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the
latter hasn't been added to the R8A7792 device tree. This patch corrects
that oversight.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge "STi late updates for v4.8" from Patrice Chotard:
- Add STi DT critical clocks declaration
- Remove SPI hack wich has dependecy with critical clocks
These 2 STi DT patches and SPI hack MUST be applied after patches
contained into Stephen Boyd's branch clk-next/clk-st-critical.
This to ensure not to break SPI.
* tag 'sti-late-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
spi: st-ssc4: Remove 'no clocking' hack
ARM: sti: stih410-clocks: Identify critical clocks
ARM: sti: stih407-family: Supply defines for CLOCKGEN A0
clk: st: clkgen-pll: Detect critical clocks
clk: st: clkgen-fsyn: Detect critical clocks
clk: st: clk-flexgen: Detect critical clocks
Currently, we check cpuidle_ops.suspend every time when entering a
low-power idle state. But this check could be avoided in this hot path
by moving it into arm_cpuidle_read_ops() to reduce arm_cpuidle_suspend
overhead a bit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Let's assume cpuidle_ops exists but it doesn't implement the according
init callback, current arm_cpuidle_init() will return success to its
caller, but in fact it should return -EOPNOTSUPP.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When doing dma allocation with IOMMU the __iommu_alloc_atomic() was
used even when the system was coherent. However, this function
allocates from a non-cacheable pool, which is fine when the device is
not cache coherent but won't work as expected in the device is cache
coherent. Indeed, the CPU and device must access the memory using the
same cacheability attributes.
Moreover when the devices are coherent, the mmap call must not change
the pg_prot flags in the vma struct. The arm_coherent_iommu_mmap_attrs
has been updated in the same way that it was done for the arm_dma_mmap
in commit 55af8a91640d ("ARM: 8387/1: arm/mm/dma-mapping.c: Add
arm_coherent_dma_mmap").
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When a L2 cache controller is used in a system that provides hardware
coherency, the entire outer cache operations are useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
controller and the Cortex-A9.
In the current kernel implementation, the outer cache flush range
operation is triggered by the dma_alloc function.
This operation can be take place during runtime and in some
circumstances may lead to the PCIe/PL310 deadlock on Armada 375/38x
SoCs.
This patch extends the __dma_clear_buffer() function to receive a
boolean argument related to the coherency of the system. The same
things is done for the calling functions.
Reported-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The workaround for both errata is to set bit 24 in the diagnostic
register. There are no known end-user bugs solved by fixing this
errata, but the fix is trivial and it seems sane to apply it.
The arguments for why this needs to be in the kernel are similar to the
arugments made in the patch "Workaround errata A12 818325/852422 A17
852423".
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This erratum has a very simple workaround (set a bit in a register), so
let's apply it. Apparently the workaround's downside is a very slight
power impact.
Note that applying this errata fixes deadlocks that are easy to
reproduce with real world applications.
The arguments for why this needs to be in the kernel are similar to the
arugments made in the patch "Workaround errata A12 818325/852422 A17
852423".
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There are several similar errata on Cortex A12 and A17 that all have the same workaround: setting bit[12] of the Feature Register.
Technically the list of errata are:
- A12 818325: Execution of an UNPREDICTABLE STR or STM instruction
might deadlock. Fixed in r0p1.
- A12 852422: Execution of a sequence of instructions might lead to
either a data corruption or a CPU deadlock. Not fixed in any A12s
yet.
- A17 852423: Execution of a sequence of instructions might lead to
either a data corruption or a CPU deadlock. Not fixed in any A17s
yet.
Since A12 got renamed to A17 it seems likely that there won't be any
future Cortex-A12 cores, so we'll enable for all Cortex-A12.
For Cortex-A17 I believe that all known revisions are affected and that all knows revisions means <= r1p2. Presumably if a new A17 was
released it would have this problem fixed.
Note that in <https://patchwork.kernel.org/patch/4735341/> folks
previously expressed opposition to this change because:
A) It was thought to only apply to r0p0 and there were no known r0p0
boards supported in mainline.
B) It was argued that such a workaround beloned in firmware.
Now that this same fix solves other errata on real boards (like
rk3288) point A) is addressed.
Point B) is impossible to address on boards like rk3288. On rk3288
the firmware doesn't stay resident in RAM and isn't involved at all in
the suspend/resume process nor in the SMP bringup process. That means
that the most the firmware could do would be to set the bit on "core
0" and this bit would be lost at suspend/resume time. It is true that
we could write a "generic" solution that saved the boot-time "core 0"
value of this register and applied it at SMP bringup / resume time.
However, since this register (described as the "Feature Register" in
errata) appears to be undocumented (as far as I can tell) and is only
modified for these errata, that "generic" solution seems questionably
cleaner. The generic solution also won't fix existing users that
haven't happened to do a FW update.
Note that in ARM64 presumably PSCI will be universal and fixes like
this will end up in ATF. Hopefully we are nearing the end of this
style of errata workaround.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some cleanups to existing device tree sources and add Toradex Apalis TK1
support.
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Merge tag 'tegra-for-4.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Merge "ARM: tegra: Device tree changes for v4.8-rc1" from Thierry Reding:
Some cleanups to existing device tree sources and add Toradex Apalis TK1
support.
* tag 'tegra-for-4.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Initial support for Apalis TK1
ARM: tegra: Remove commas from unit addresses on Tegra124
ARM: tegra: Import latest Jetson TK1 spreadsheet
ARM: tegra: Add spaces around = in properties
ARM: tegra: Fix a couple of DTC warnings
of machine-local files and boardfile-type data for regulators
and ASoC.
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Merge tag 'ux500-cleanup-bundle' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/drivers
Merge "Ux500 cleanups from Arnd" from Linus Walleij:
This is a set of cleanups for the Ux500 that reduce the number
of machine-local files and boardfile-type data for regulators
and ASoC.
* tag 'ux500-cleanup-bundle' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: consolidate base platform files
ARM: ux500: move soc_id driver to drivers/soc
ARM: ux500: call ux500_setup_id later
ARM: ux500: consolidate soc_device code in id.c
ARM: ux500: remove cpu_is_u* helpers
ARM: ux500: use CLK_OF_DECLARE()
ARM: ux500: move l2x0 init to .init_irq
mfd: db8500 stop passing around platform data
ASoC: ab8500-codec: remove platform data based probe
ARM: ux500: move ab8500_regulator_plat_data into driver
ARM: ux500: remove unused regulator data
Kconfig dependencies for v4.8 merge window. Otherwise things
like USB Ethernet on omap3 beagle, omap4 panda and omap5-uevm
won't work without manual configuration.
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Merge tag 'omap-for-v4.8/defconfig-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig
Merge "omap2plus_defconfig fix for v4.8 merge window" from Tony Lindgren:
A defconfig update for omap2plus_defconfig to fix changed USB
Kconfig dependencies for v4.8 merge window. Otherwise things
like USB Ethernet on omap3 beagle, omap4 panda and omap5-uevm
won't work without manual configuration.
* tag 'omap-for-v4.8/defconfig-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: omap2plus_defconfig: Fix USB selection to keep Ethernet working
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution,
we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a
more generic for the STi SoCs family
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Merge tag 'sti-soc-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/soc
Merge "STi SoC changes for v4.8" from Patrice Chotard:
- Add a dummy L2 cache's write_sec callback as in non secure mode execution,
we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a
more generic for the STi SoCs family
* tag 'sti-soc-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: sti: Implement dummy L2 cache's write_sec
ARM: STi: Update machine _namestr to be more generic.
The change to simplify of_platform_populate() had an unintended
side-effect of introducing a build warning on s3c64xx:
In file included from arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c:18:0:
arch/arm/mach-s3c64xx/common.h:27:30: error: 'struct device_node' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
This adds a forward-declaration for the structure name in the
header to avoid the warning.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 850bea2335e4 ("arm: Remove unnecessary of_platform_populate with default match table")
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
commit 6bce5efd4424 ("ARM: davinci: remove unused davinci-i2s pdata")
removed all instances of davinci-i2s pdata. However, on DM365 EVM,
the same platform data is passed to the voicecodec present on that
device.
This causes build breakage when voicecodec support is enabled:
arch/arm/mach-davinci/board-dm365-evm.c:764:17: error: 'dm365_evm_snd_data' undeclared (first use in this function)
voicecodec driver does not use the platform data as well, and
it is safe to remove it.
Fixes: 6bce5efd4424 ("ARM: davinci: remove unused davinci-i2s pdata")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Install the callbacks via the state machine.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: rt@linutronix.de
Link: http://lkml.kernel.org/r/20160713153333.503198935@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Noticed while making a copy of these files to tools/ where those kernel
files were being directly accessed, which we're not allowing anymore to
avoid that changes in the kernel side break tooling.
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Eric Auger <eric.auger@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Wang Nan <wangnan0@huawei.com>
Link: http://lkml.kernel.org/n/tip-82thftcdhj2j5wt6ir4vuyhk@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Lots of platforms contain clocks which if turned off would prove fatal.
The only way to recover is to restart the board(s). This driver takes
references to clocks which are required to be always-on. The Common
Clk Framework will then take references to them. This way they will
not be turned off during the clk_disabled_unused() procedure.
In this patch we are identifying clocks, which if gated would render
the STiH410 development board unserviceable.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The cpu.c and cache-l2x0.c files hold only two or three simple
functions each, and they are all called from the machine
descriptors, so we can just move them all into the same file
for simplicity and consistency.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As the ux500 id code is basically a standalone driver, we can move it
out of the arch code into drivers/soc/ux500.
This is a user-visible change, as it moves all the devices in sysfs
from /sys/devices/soc0/ to /sys/devices/ and leaves the soc0 node as a
separate device.
Originally the idea was to put all on-chip devices under the soc node,
and ux500 was the first platform to have this device, but later platforms
almost all didn't follow that pattern, so this makes the platform do
the same thing as everyone else.
Since the platform is really obsolete now, I am optimistic that nothing
will break after moving the devices around.
As the SoC driver no longer has access to the private header files,
I'm changing the code to instead look up the address of the backupram
from devicetree, which is a good idea anyway.
Finally, having a separate Kconfig symbol means the driver is now
optional and could even be a loadable module rather than always being
built-in if we allowed that for soc_device.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[Fixup mising Makefile, fixup BB_UID_BASE to fc0]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ux500_setup_id is currently called from u8500_map_io(), which is
really early, but nothing relies on the ID any more, other than
a printk message that is not really all that important to
have early during boot.
If we move the call to ux500_setup_id() into ux500_soc_device_init(),
that file becomes usuable almost entirely standalone, and we can kill
off the u8500_map_io() callback as it just does the default
debug_ll_io_init() now.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nothing else uses the global dbx500_asic_id structure, so
we can merge the two small files that reference it into one.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These functions are all unused now and can be removed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ux500 DT support predates the CLK_OF_DECLARE macro and calls
directly into the clk driver from platform code.
Converting this to CLK_OF_DECLARE makes the code much nicer and
similar to how modern platforms do it today. It also removes the
last user of cpu_is_u8500_family() etc.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The generic IRQ init function also enables the l2 cache
implicitly when the machine descriptor sets an .l2c_aux_mask.
Let's use that on ux500 and remove the ux500_l2x0_init()
along with the cpu_is_u8500_family checks.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Except for the constant DB8500_PRCMU_FW_VERSION_OFFSET number, nothing
is ever passed through the platform data and used in a driver, so we
can simply stop passing it around.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is only one instance of ab8500_regulator_platform_data, and it's
safe to assume we won't ever merge another one, so it's rather pointless
to pass it through multiple levels of platform data pointers.
This moves the structure and everything referenced by it into the
driver that uses it.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most of the board-mop500-regulators.c file is never referenced and
can simply be removed.
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The clearfog DTS should not be defining the on-board phy, this device
is located on the microsom. Remove the duplicated definition.
Reported-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The smartq_map_io() and smartq_machine_init() functions are used by both
SmartQ 5 and SmartQ 7 machines and exported via the mach-smartq.h header
file. However that header file is not included by the mach-smartq.c file
that implements them, causing sparse warnings.
Include mach-smartq.h from mach-smartq.c to fix these warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds the device tree to support Toradex Apalis TK1 a
computer on module which can be used on different carrier boards.
The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality which is not yet
supported. Anything that is not self contained on the module is disabled
by default.
The device tree for the Evaluation Board includes the module's device
tree and enables the supported peripherals of the carrier board (the
Evaluation Board supports almost all of them).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove commas from unit addresses as suggested by Rob Herring upon me
posting initial Apalis TK1 support:
http://article.gmane.org/gmane.linux.ports.tegra/26608
Please keep the remaining 0, notation on the GPU node in place as a
former mainline U-Boot version was looking for that particular notation
in order to perform required fix-ups on it.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.
The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
In a configuration that enables CONFIG_UBSAN_SANITIZE_ALL, I am getting
a section mismatch warning for tegra20:
WARNING: arch/arm/mach-tegra/built-in.o(.data+0x6e0): Section mismatch in reference from the variable board_init_funcs to the function .init.text:paz00_init()
The array is no longer useful here since there is only one entry,
so we can simply call the function directly after checking
of_machine_is_compatible(). This fixes the section mismatch
and is easier to read.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This seems to have been copied and pasted since the beginning of time,
though only until Tegra124, likely because that DT was written from
scratch or it was fixed along the way.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch implements the write_sec callback that handle PL310
secure registers writes.
This callback is just a stub for now, to avoid system crash.
Later, it could handle SMC calls so that TZ handles the needed writes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This string is used by dump_stack and as we now support
more SoC's than just STiH415/6 it is misleading to have
the current string in the stack trace.
This patch updates it to be more generic for the STi
family of SoCs.
So instead of looking like this
[ 271.672555] Hardware name: STiH415/416 SoC with Flattened Device Tree
[ 271.678998] [<c0310490>] (unwind_backtrace) from [<c030bb54>] (show_stack+0x10/0x14)
[ 271.686746] [<c030bb54>] (show_stack) from [<c058bc4c>] (dump_stack+0x98/0xac)
[snip]
it now looks like this:
[ 2.669879] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.6.0-rc3-00026-g38a1ce6-dirty #76
[ 2.677973] Hardware name: STi SoC with Flattened Device Tree
[ 2.683723] [<c0310490>] (unwind_backtrace) from [<c030bb54>] (show_stack+0x10/0x14)
[ 2.691472] [<c030bb54>] (show_stack) from [<c058bc0c>] (dump_stack+0x98/0xac)
[snip]
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
The red led on the Bananapi M1+ is wired to light up as soon as the
board is powered, and continues to be lit while the GPIO is floating.
Rename the LED to "pwr", remove the default trigger, and mark it as
default on.
Also fix the pinmux node that was specifying a different pin for this
LED.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dts file uses "bananapi" for some labels and "bananapim1plus" for
other. Use the shortened "bpi_m1p" suffix for all board specific labels.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The bananapi-m1-plus dts file was indented using 4 spaces, without
tabs. This does not match the code style.
Reindent the whole file before we do anything else.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Lamobo R1 has a headphone jack for audio output, and an onboard
microphone. These are tied to the SoC's internal audio codec.
Enable the audio codec.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
