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In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
mezzanine.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
and enable it in board dts for usage of 96boards LS mezzanine board.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add cpu and cluster level's low power state for Hi6220.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add sp804 timer for hi6220, so it can be used as broadcast timer.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
On Hi6220, below memory regions in DDR have specific purpose:
0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
0x06df,f000 - 0x06df,ffff: For mailbox message data;
0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
This patch reserves these memory regions in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Juno development platform has an external expansion bus which can
be used for additional hardware (e.g. LogicTile Express daughterboards).
Add this bus to the Juno base device-tree.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
With CONFIG_PROVE_LOCKING, CONFIG_DEBUG_LOCKDEP and CONFIG_TRACE_IRQFLAGS
enabled, lockdep will compare current->hardirqs_enabled with the flags from
local_irq_save().
When a debug exception occurs, interrupts are disabled in entry.S, but
lockdep isn't told, resulting in:
DEBUG_LOCKS_WARN_ON(current->hardirqs_enabled)
------------[ cut here ]------------
WARNING: at ../kernel/locking/lockdep.c:3523
Modules linked in:
CPU: 3 PID: 1752 Comm: perf Not tainted 4.5.0-rc4+ #2204
Hardware name: ARM Juno development board (r1) (DT)
task: ffffffc974868000 ti: ffffffc975f40000 task.ti: ffffffc975f40000
PC is at check_flags.part.35+0x17c/0x184
LR is at check_flags.part.35+0x17c/0x184
pc : [<ffffff80080fc93c>] lr : [<ffffff80080fc93c>] pstate: 600003c5
[...]
---[ end trace 74631f9305ef5020 ]---
Call trace:
[<ffffff80080fc93c>] check_flags.part.35+0x17c/0x184
[<ffffff80080ffe30>] lock_acquire+0xa8/0xc4
[<ffffff8008093038>] breakpoint_handler+0x118/0x288
[<ffffff8008082434>] do_debug_exception+0x3c/0xa8
[<ffffff80080854b4>] el1_dbg+0x18/0x6c
[<ffffff80081e82f4>] do_filp_open+0x64/0xdc
[<ffffff80081d6e60>] do_sys_open+0x140/0x204
[<ffffff80081d6f58>] SyS_openat+0x10/0x18
[<ffffff8008085d30>] el0_svc_naked+0x24/0x28
possible reason: unannotated irqs-off.
irq event stamp: 65857
hardirqs last enabled at (65857): [<ffffff80081fb1c0>] lookup_mnt+0xf4/0x1b4
hardirqs last disabled at (65856): [<ffffff80081fb188>] lookup_mnt+0xbc/0x1b4
softirqs last enabled at (65790): [<ffffff80080bdca4>] __do_softirq+0x1f8/0x290
softirqs last disabled at (65757): [<ffffff80080be038>] irq_exit+0x9c/0xd0
This patch adds the annotations to do_debug_exception(), while trying not
to call trace_hardirqs_off() if el1_dbg() interrupted a task that already
had irqs disabled.
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Since commit 1cf4f629d9d2 ("cpu/hotplug: Move online calls to
hotplugged cpu") it is ensured that callbacks of CPU_ONLINE and
CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this SMP
function calls are no longer required.
Replace smp_call_function_single() with a direct call of
hw_breakpoint_reset(). To keep the calling convention, interrupts are
explicitly disabled around the call.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Since commit 1cf4f629d9d2 ("cpu/hotplug: Move online calls to
hotplugged cpu") it is ensured that callbacks of CPU_ONLINE and
CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this SMP
function calls are no longer required.
Replace smp_call_function_single() with a direct call to
clear_os_lock(). The function writes the OSLAR register to clear OS
locking. This does not require to be called with interrupts disabled,
therefore the smp_call_function_single() calling convention is not
preserved.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The mapping of the kernel consist of four segments, each of which is mapped
with different permission attributes and/or lifetimes. To optimize the TLB
and translation table footprint, we define various opaque constants in the
linker script that resolve to different aligment values depending on the
page size and whether CONFIG_DEBUG_ALIGN_RODATA is set.
Considering that
- a 4 KB granule kernel benefits from a 64 KB segment alignment (due to
the fact that it allows the use of the contiguous bit),
- the minimum alignment of the .data segment is THREAD_SIZE already, not
PAGE_SIZE (i.e., we already have padding between _data and the start of
the .data payload in many cases),
- 2 MB is a suitable alignment value on all granule sizes, either for
mapping directly (level 2 on 4 KB), or via the contiguous bit (level 3 on
16 KB and 64 KB),
- anything beyond 2 MB exceeds the minimum alignment mandated by the boot
protocol, and can only be mapped efficiently if the physical alignment
happens to be the same,
we can simplify this by standardizing on 64 KB (or 2 MB) explicitly, i.e.,
regardless of granule size, all segments are aligned either to 64 KB, or to
2 MB if CONFIG_DEBUG_ALIGN_RODATA=y. This also means we can drop the Kconfig
dependency of CONFIG_DEBUG_ALIGN_RODATA on CONFIG_ARM64_4K_PAGES.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Keeping .head.text out of the .text mapping buys us very little: its actual
payload is only 4 KB, most of which is padding, but the page alignment may
add up to 2 MB (in case of CONFIG_DEBUG_ALIGN_RODATA=y) of additional
padding to the uncompressed kernel Image.
Also, on 4 KB granule kernels, the 4 KB misalignment of .text forces us to
map the adjacent 56 KB of code without the PTE_CONT attribute, and since
this region contains things like the vector table and the GIC interrupt
handling entry point, this region is likely to benefit from the reduced TLB
pressure that results from PTE_CONT mappings.
So remove the alignment between the .head.text and .text sections, and use
the [_text, _etext) rather than the [_stext, _etext) interval for mapping
the .text segment.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Apart from the arm64/linux and EFI header data structures, there is nothing
in the .head.text section that must reside at the beginning of the Image.
So let's move it to the .init section where it belongs.
Note that this involves some minor tweaking of the EFI header, primarily
because the address of 'stext' no longer coincides with the start of the
.text section. It also requires a couple of relocated symbol references
to be slightly rewritten or their definition moved to the linker script.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Replace the poorly defined term chunk with segment, which is a term that is
already used by the ELF spec to describe contiguous mappings with the same
permission attributes of statically allocated ranges of an executable.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Now that the vmemmap region has been redefined to cover the linear region
rather than the entire physical address space, we no longer need to
perform a virtual-to-physical translation in the implementaion of
virt_to_page(). This restricts virt_to_page() translations to the linear
region, so redefine virt_addr_valid() as well.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This moves the vmemmap region right below PAGE_OFFSET, aka the start
of the linear region, and redefines its size to be a power of two.
Due to the placement of PAGE_OFFSET in the middle of the address space,
whose size is a power of two as well, this guarantees that virt to
page conversions and vice versa can be implemented efficiently, by
masking and shifting rather than ordinary arithmetic.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Before restricting virt_to_page() to the linear mapping, ensure that
the text patching code does not use it to resolve references into the
core kernel text, which is mapped in the vmalloc area.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The zero page is statically allocated, so grab its struct page pointer
without using virt_to_page(), which will be restricted to the linear
mapping later.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The implementation of free_initmem_default() expects __init_begin
and __init_end to be covered by the linear mapping, which is no
longer the case. So open code it instead, using addresses that are
explicitly translated from kernel virtual to linear virtual.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The translation performed by virt_to_page() is only valid for linear
addresses, and kernel symbols are no longer in the linear mapping.
So perform the __pa() translation explicitly, which does the right
thing in either case, and only then translate to a struct page offset.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This removes the relocate_initrd() implementation and invocation, which are
no longer needed now that the placement of the initrd is guaranteed to be
covered by the linear mapping.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Instead of going out of our way to relocate the initrd if it turns out
to occupy memory that is not covered by the linear mapping, just add the
initrd to the linear mapping. This puts the burden on the bootloader to
pass initrd= and mem= options that are mutually consistent.
Note that, since the placement of the linear region in the PA space is
also dependent on the placement of the kernel Image, which may reside
anywhere in memory, we may still end up with a situation where the initrd
and the kernel Image are simply too far apart to be covered by the linear
region.
Since we now leave it up to the bootloader to pass the initrd in memory
that is guaranteed to be accessible by the kernel, add a mention of this to
the arm64 boot protocol specification as well.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This reverts commit 36e5cd6b897e17d03008f81e075625d8e43e52d0, since the
section alignment is now guaranteed by construction when choosing the
value of memstart_addr.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This redefines ARM64_MEMSTART_ALIGN in terms of the minimal alignment
required by sparsemem vmemmap. This comes down to using 1 GB for all
translation granules if CONFIG_SPARSEMEM_VMEMMAP is enabled.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
After choosing memstart_addr to be the highest multiple of
ARM64_MEMSTART_ALIGN less than or equal to the first usable physical memory
address, we clip the memblocks to the maximum size of the linear region.
Since the kernel may be high up in memory, we take care not to clip the
kernel itself, which means we have to clip some memory from the bottom if
this occurs, to ensure that the distance between the first and the last
usable physical memory address can be covered by the linear region.
However, we fail to update memstart_addr if this clipping from the bottom
occurs, which means that we may still end up with virtual addresses that
wrap into the userland range. So increment memstart_addr as appropriate to
prevent this from happening.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXDIe4AAoJEPOmecmc0R2B3acH/3U9VHCGVy7w5RNl/UISe6Eu
og7QZyy8r8dNw+bk9EX8x9AyqkN4bHAfAqg+Pc+JvxOeqmTjxFqPqZKWjEUQ8BOw
SPsJE0ZeRRYAvp1OYfR1ATGwRQDvJq+DaKtb9d8S6ZdYdwXWR/JhkXiCxpQGEqAO
TV82csxc86T+F+GJN63uk0UVfnZhzFtCJ6zSWBVyEpiUYxeQwTSkxjVUUJagOJLT
Wb/0qgD2b8L1Xs8Flj0zVwAsvNIBKlxsaXzhN9EBD9pnHDQJ1l2cU2EdsQtWCwlE
9ic2kwYFlgTrCAo1FITWFgyUTFLnuGcrfn2QIBIWK1X6TBJuYauGzslJEE96luw=
=zT4u
-----END PGP SIGNATURE-----
Merge tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
This contains the rk3368-geekbox as new board, mailbox device
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.
* tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
Documentation: devicetree: rockchip: Document rk3368-GeekBox
arm64: dts: rockchip: Add rk3368 GeekBox dts
arm64: dts: rockchip: Clean up gpio-keys nodes
dt-bindings: Add vendor prefix for GeekBuying.com
arm64: dts: rockchip: Add rk3368 mailbox device nodes
arm64: dts: rockchip: remove broken-cd from emmc and sdio
arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
Add initial dtsi file to support lg1312 SoC which based on
Cortex-A53. Also add dts file to support lg1312 reference board
which based on lg1312 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch introduces ARCH_LG1K to enable LG Electronics's LG1K SoC
family in Kconfig.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use USB3.0 fallback compatibility string in DT for r8a7795 SoC
* Add CAN support to DT for r8a7795 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXAb1iAAoJENfPZGlqN0++HZMP/1zD/pKDsMdDy6RpK8zBp6x+
jNT8aiq6B6Ss7dSsFp6c25wE7xJgfgeNNfIupslv3KL3AhcX613v0UbZLSRCxfBr
wKmbFq0LszecNpYydQmgPClqyV3t5ldu9gI+zDY1MoGqGMnmceWILiWcRIfnzWqr
wZaKdZ6vB1CILwOU/WMG4/TZLMag3OIMMRb6zTvtN/GO/OEVdbXU9Mdnkd9rCbtQ
qYOIUzMPPvoOzpwCudVMv7S+2Wa2hsDwDpyYoEZfBtqw8N7GkJ0te5yS3puvJiXF
TYB4KYgld2Dp1LdaS8wnZIXVXlM5fEFedcLQhdOq70DaMBZpotiwxzxpdkRIjYcX
TM3ZycQm91z2urP21gpUGgK5sON6zZOoNiWxwXs4q051ofyphrdfHnxCyxPUYsmd
PK/kUKNyTqyBSLcHkeedePJDaL7Ymk/Ij2ggjNXb1OBBcSpR1YUB0jcKuICR/AwJ
19IRXQu4ceHaMHTPqqpjwtHTVOPDQBzKXeqUSXLZELWpEdbvlpD6sJF2iKc9UsdG
juAH+LmWqWVZx1QQoAA+VqLY3XQ5glr/PwKy0sS5Is7JLOdC8v05sDdJ8oZ/jEnl
Ka+g3FUPKOpCGeN5qH59b0v0cgUbfuq18BP1bgOsWTGKBK2zSK5IAS00qquIx/wq
H8x3JTXDecJptEFgGurp
=m8DD
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM64 Based SoC DT Updates for v4.7
* Use USB3.0 fallback compatibility string in DT for r8a7795 SoC
* Add CAN support to DT for r8a7795 SoC
* tag 'renesas-arm64-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: Use USB3.0 fallback compatibility string
arm64: dts: r8a7795: Add CAN support
arm64: dts: r8a7795: Add CAN external clock support
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use generic pinctrl properties in DT for salvator-x board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXAbzyAAoJENfPZGlqN0++JtQP/3C5RzIRZs4ul1cZXo9nGAhs
9qqB+ew/vDm17LKOIHNgZpWVyJkVfKYH7YhydUgAmk9WncStNjd5EStvLtBwqd0w
3enSKOYBA7kqoEnREY7y/D1WQLZxUfc/aYObCd113HzwWk/TaRCLphCjf+jozc9E
n5WtsgEBvP5gzqFaDPxnii92W1McIgnuZxcO5xj4vhxWhPr6SBfsksyJ8Luj7heh
GnqittFUkHJho5rGGyQz+rNg2fnqfyxL/9S0D1Ss7HDUAjCeSprYNqvavQkri+si
Avw/tI9A6uv2tHKtMmOAq+xrhx56LOfayaW36+Yl6XOf+ExwP9r/V/CFaQK11VZW
l3NFBzy+q/8b5UtbmbW+efl3Q80/ah+IenfX+jJdyngnN87b+K75qBqSp80h1RgA
5a32dgWAdMBXoTyUVGaxi3+MQ2b2DbLijduIFH0k5lX9xqfawIHLUUj+i3MGo5em
WPui8kQ8bQpTt6KDxRtJiSLYAZpa+WBm6RJXIFg5ayBB7kYkC0t7aPLuErcSFoH8
oThU+2pKBwxLNaZqAhnrrjP1kIDU50d+0YSMvJ3bfpi22azGjHpq5GUCsV/F6yn7
x/zlT1LyoQ3fl9IG4HwxNY3i/bLYnCQqiJf667QqqKxzQ2OwsNVl5alPWnxf6FbZ
LuQAioF5gkwpepqeR0IC
=bcz4
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC Cleanup for v4.7
* Use generic pinctrl properties in DT for salvator-x board
* tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: salvator-x: use generic pinctrl properties
Signed-off-by: Olof Johansson <olof@lixom.net>
We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK,
one of the ARM PL022 SPI host has Silabs si3226x slic connected
to chip-select #0 whereas second ARM PL022 SPI host has Atmel
AT25 EEPROM connected to chip-select #0.
This patch adds ARM PL022, Silabs si3226x, and Atmel AT25
DT nodes in NS2 DT and NS2 SVK DT respectively.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
For more readabilty and consistency with other Broadcom SoCs, we move
all NS2 clock DT nodes from main SoC DT file to a separate DT file.
We also update the license header in ns2.dtsi as-per new Broadcom
convention.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The KVM ARM64 requires GIC maintenance interrupt for VGIC emulation
so this patch adds the missing "interrupts" attribute to GIC node in
NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have one ARM PL330 DMA instance with 8 channels in
NS2 SoC. Let's enable it for NS2 in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
and Amlogic P200/P201 boards.
We also fix the memory nodes on the Vega S95 DTS.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW/B2sAAoJELyGR0S84or4+80P/j77A1ng6Q0NVAl3EZ1K0x1U
BwxaJ7NsbUpnoZMmoqOWDMdM4W2pwir2tPYJ+pJdgQnmRLc++Nmes/tGViMM7GeV
GYzARcn99gwjXqB0yZcsxTTWzZbF8kt823IW2pjw5W6Nd5CMZ/frLPSB4HjPFr7n
RntcXD7iSs4PvZqKhzYQRkYs8diLFxNZjcohv3dutrmOFY63eH8pok+Geb2TZhr7
hTJ+/wEQ34x0rg6wpSpNd2+UIaZ3o7BwL66gZUb+tCGye0oomh+lUJ0fSRYH65c7
UVdRhfYDf+2pmGsxZJC2W+ENSPxbMybkC9chOf9h7MyoeMfTUY1T+yqDM7kn+1mK
1Erzco/24ARxbWmX4v6+HTFLYiFXLgG89YYBKmlGm4HwSIvtrxfdN6wBf1lXJhXH
eWHfgd7vd1oPGvbBlC5ZqGFI+EieQOz4C3guQWLiZfVPBNep8wmryfXvtosGvqmD
n7PSHf5v6nXSI33DTn9/SVVtqJr0f2FjiLhUrTc7daTQyJQwdLynyVizhJsnNK+r
yMEF9ZsONUAfK1hws9K2PUCMa2Iw9OGcacoeXwLmmMLJ3AqXAfM+9UvgkJ5qSahy
K9FDSi426QV5EghfeRhugfngtJWu0W0JSTRp7IqftOCfEnaoDBvP8sRe6AHmavan
4qNYccKObyzxEV9bG7K1
=hEv4
-----END PGP SIGNATURE-----
Merge tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson into next/dt64
Add support for a few more Amlogic S905/GXBB based boards: Hardkernel ODROID-C2
and Amlogic P200/P201 boards.
We also fix the memory nodes on the Vega S95 DTS.
* tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson:
ARM64: dts: amlogic: Add P200/P201 boards
ARM64: dts: amlogic: add Hardkernel ODROID-C2
Documentation: devicetree: amlogic: Document P20x and ODROID-C2 boards
ARM64: dts: amlogic: update serial aliases
ARM64: dts: amlogic: Clean up Vega S95 /memory nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
A batch of fixes for -rc4, for various platforms. Nothing really
substantial and worth pointing out in particular; small fixes for various
bugs, see shortlog for details.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXDYm+AAoJEIwa5zzehBx3pP8P/1Xgh0QnJhYk/yxjeZziQcZe
9jzLKpuIs3aRhM8pcwXuKIwguxp74UkEogK16D0JUzB73ySJmVyaX2Os84RBnBLb
schb6hpRyjoc+bI9rfHMQQRsyC4NVPdxKq6+YDxl5MZkSbRnGUvEN7EUQPD7kkrb
wQfkTi8PvF9e2edehwzKwKLUxFb2R9pO/5BiEZoNjFtSe0aQIy2EfTYsfRxSkvpZ
WZagfRtjMAQfZcV5N1DkyEakNtzkbjwTbGHxbumHJ3hFZ/EaD6c6Vk+HEtDXH0Qj
50Ful4LRq4ph3/RrsOcfIfBMd8aZbo7fPAiZIDUV7rWenoKBoePLYxO1Y85WLOq8
a6UAyUzWC7osBxGeoi/nlahsDNJEeH3R+HLKIagKBHdrmw07LibuJlNj9XYPqlbz
kScZCQ+aY1t1tzOCy823wT7knBkJaORgTFXw8BgNrmPkphzaEHkjwARQxaaIHg8N
Up0sCB/l/6EZ2YX/iDbyKYt7HDGCzWbWpcfeZfxgO+EvT834iJIpTFu6mHNAvnT1
HJD94evTDAo6/K8S4z9xVHnPqevfzQzCz+TcGhbhTHLhZ/i6t+BuuazQ/KrEq7hG
NzVyAJm1xKZybcU6gPk7ZpSKA4NZhTASnfIuEeT/vhn6aSaZAHtMVMCGNfHgn77A
fegXqmmQP4019pwSz/3B
=5GPE
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A batch of fixes for -rc4, for various platforms.
Nothing really substantial and worth pointing out in particular; small
fixes for various bugs, see shortlog for details"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: sa1100: remove references to the defunct handhelds.org
bus: uniphier-system-bus: fix condition of overlap check
ARM: uniphier: drop weird sizeof()
ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type
ARM: OMAP: Correct interrupt type for ARM TWD
ARM: DRA722: Add ID detect for Silicon Rev 2.0
ARM: dts: am43xx: fix edma memcpy channel allocation
ARM: dts: AM43x-epos: Fix clk parent for synctimer
ARM: OMAP2: Fix up interconnect barrier initialization for DRA7
documentation: Fix pinctrl documentation for Meson8 / Meson8b
ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
ARM: mvebu: Correct unit address for linksys
bus: mvebu-mbus: use %pa to print phys_addr_t
arm64: dts: vulcan: Update PCI ranges
ARM: u8500_defconfig: turn on the Synaptics RMI4 driver
ARM: pxa: fix the number of DMA requestor lines
ARM: OMAP2+: hwmod: Fix updating of sysconfig register
ARM: OMAP2+: Use srst_udelay for USB on dm814x
Currently, we check two pointers: cpu_ops and cpu_suspend on every idle
state entry. These pointers check can be avoided:
If cpu_ops has not been registered, arm_cpuidle_init() will return
-EOPNOTSUPP, so arm_cpuidle_suspend() will never have chance to
run. In other word, the cpu_ops check can be avoid.
Similarly, the cpu_suspend check could be avoided in this hot path by
moving it into arm_cpuidle_init().
I measured the 4096 * time from arm_cpuidle_suspend entry point to the
cpu_psci_cpu_suspend entry point. HW platform is Marvell BG4CT STB
board.
1. only one shell, no other process, hot-unplug secondary cpus, execute
the following cmd
while true
do
sleep 0.2
done
before the patch: 1581220ns
after the patch: 1579630ns
reduced by 0.1%
2. only one shell, no other process, hot-unplug secondary cpus, execute
the following cmd
while true
do
md5sum /tmp/testfile
sleep 0.2
done
NOTE: the testfile size should be larger than L1+L2 cache size
before the patch: 1961960ns
after the patch: 1912500ns
reduced by 2.5%
So the more complex the system load, the bigger the improvement.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
There are some new cpu features which can be identified by id_aa64mmfr2,
this patch appends all fields of it.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch adds device tree nodes for pdma0 and pdma1 controllers
found on exynos7 SoCs.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch enables PL330 DMA controller found on exynos7 SoCs.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls2080a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls1043a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
