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72 Commits

Author SHA1 Message Date
Likun Gao
9503a944e7 drm/amdgpu: enable cgcg and cgls for GC 11_0_2 
Enable GFX CGCG and CGLS for GFX v11_0_2.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:53:00 -04:00
James Zhu
ec9db74e1a drm/amdgpu/vcn: enable VCN DPG mode for VCN4_0_4 
Enable VCN DPG mode for VCN4_0_4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:52:21 -04:00
James Zhu
143a34a0ac drm/amdgpu/vcn: enable VCN PG for VCN4_0_4 
Enable VCN PG for VCN4_0_4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:52:18 -04:00
James Zhu
7ece9314a4 drm/amdgpu/vcn: enable VCN CG for VCN4_0_4 
Enable VCN CG for VCN4_0_4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:52:16 -04:00
James Zhu
ebac66a328 drm/amdgpu/jpeg: enable JPEG PG for VCN4_0_4 
Enable JPEG PG for VCN4_0_4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:52:14 -04:00
James Zhu
71dae22143 drm/amdgpu/jpeg: enable JPEG CG for VCN4_0_4 
Enable JPEG CG for VCN4_0_4.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:52:12 -04:00
Flora Cui
92fd215314 drm/amdgpu: add soc21 support for GC 11.0.2 
Add initial soc21 support.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:24 -04:00
Evan Quan
d386f64588 drm/amdgpu: enable clock gating for HDP 6.0 
Enable HDP 6.0 clock gating.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:21 -04:00
Evan Quan
2013906955 drm/amdgpu: enable clock gating for IH 6.0 
Enable IH 6.0 clock gating.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:17 -04:00
Evan Quan
7ccf6eb003 drm/amdgpu: enable MGCG and LS for MMHUB 3.0 
Enable MMHUB 3.0 MGCG and LS features.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:14 -04:00
Evan Quan
c649ed054a drm/amdgpu: enable MGCG and LS for ATHUB 3.0 
Enable ATHUB 3.0 MGCG and LS features.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:51:11 -04:00
Evan Quan
915b5ce774 drm/amdgpu: enable more GFX clockgating features for GC 11.0.0 
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-05 16:50:58 -04:00
James Zhu
9ac0edaa0f drm/amdgpu: add vcn_4_0_0 video codec query 
Add vcn_4_0_0 video codec query.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:56 -04:00
James Zhu
04270390fe drm/amdgpu/vcn: enable vcn4 dpg mode 
Enable vcn4 dpg mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:56 -04:00
James Zhu
7c507d35a5 drm/amdgpu/jpeg: enable JPEG PG and CG for VCN4_0_0 
Enable JPEG PG and CG for VCN4_0_0.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:56 -04:00
Leo Liu
8b719b968f drm/amdgpu: enable VCN4 PG and CG for VCN4_0_0 
Most of the tiles can be power/clock gated.

Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:56 -04:00
Evan Quan
b21348a28b drm/amdgpu: enable fgcg for soc21 
Enable Fine Grained Clock Gating on soc21 asics.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:54 -04:00
Evan Quan
390db4b84a drm/amdgpu: enable GFX CGCG/CGLS for GC11.0.0 
Enable GFX CGCG (coarse grained clockgating) and
CGLS (coarse grained light sleep) for GC11.0.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:54 -04:00
Jack Xiao
fd0ed91ae8 drm/amdgpu: correct cp doorbell range 
1. move MES doorbell inside the mec doorbell range,
   for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
   fw can correctly detect gfx/compute work load to enter/exit
   power saving state.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-and-acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:53 -04:00
Jack Xiao
b608e785e1 drm/amdgpu: allocate doorbell index for mes kiq 
Allocate a doorbell index for mes kiq queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 10:43:49 -04:00
Evan Quan
a6dec86840 drm/amdgpu/soc21: enable ATHUB and MMHUB PG 
Enable ATHUB and MMHUB powergating.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-05-04 09:58:59 -04:00
Stanley.Yang
71199aa47b drm/amdgpu: add soc21 common ip block v2 
This adds soc21 common ip block support

Changed from v1:
Switch WREG32/RREG32_PCIE to use indirect reg access
helper for sco15 and onwards

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2022-04-28 17:48:40 -04:00