4249 Commits

Author SHA1 Message Date
Alexandre Torgue
e2f3cf18c3 pinctrl: stm32: add suspend/resume management
During power sequence, GPIO hardware registers could be lost if the power
supply is switched off. Each device using pinctrl API is in charge of
managing pins during suspend/resume sequences. But for pins used as gpio or
irq stm32 pinctrl driver has to save the hardware configuration.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-24 13:21:15 +02:00
Amelie Delaunay
ec2e0f4f00 pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined
When CONFIG_GPIO_OF is not defined, struct gpio_chip 'of_node' member does
not exist:
drivers/pinctrl/pinctrl-stmfx.c: In function 'stmfx_pinctrl_probe':
drivers/pinctrl/pinctrl-stmfx.c:652:17: error: 'struct gpio_chip' has no member named 'of_node'
     pctl->gpio_chip.of_node = np;

Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-24 10:09:28 +02:00
Linus Walleij
b672a87ae5 pinctrl: core: Do not add device links for hogs
Hogs would create circular device links, so do not link
the device to itself.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-24 10:08:04 +02:00
Benjamin Gaignard
c6045b4e3c pinctrl: stmfx: enable links creations
Set create_link to inform pinctrl core that stmfx wants to create
link with its consumers.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:35:48 +02:00
Benjamin Gaignard
036f394dd7 pinctrl: Enable device link creation for pin control
A pin controller may want to create a link between itself
and its clients to be sure of suspend/resume call ordering.

Introduce link_consumers field in pinctrl_desc structure to let
pinctrl core knows that controller expect to create a link.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
[Renamed create_link to link_consumers]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:34:54 +02:00
Doug Berger
ee11f864f1 pinctrl: bcm: Allow PINCTRL_BCM2835 for ARCH_BRCMSTB
ARCH_BRCMSTB needs to use the BCM2835 pin controller for chips
like BCM7211 which adopted that pin controller for GPIO. This
commit makes the option menu configurable with default enabled
for ARCH_BRCMSTB and ARCH_BCM2835.

Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Guillaume La Roque
2484ae57c2 pinctrl: meson: g12a: add DS bank value
add drive-strength bank regiter and bit value for G12A SoC

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Guillaume La Roque
6ea3e3bbef pinctrl: meson: add support of drive-strength-microamp
drive-strength-microamp is a new feature needed for G12A SoC.
the default DS setting after boot is usually 500uA and it is not enough for
many functions. We need to be able to set the drive strength to reliably
enable things like MMC, I2C, etc ...

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Guillaume La Roque
9959d9a747 pinctrl: meson: Rework enable/disable bias part
rework bias enable/disable part to prepare drive-strength integration
no functional changes

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Guillaume La Roque
c08e7e4c8a pinctrl: generic: add new 'drive-strength-microamp' property support
Add drive-strength-microamp property support to allow drive strength in uA

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Wen Yang
3c89c70634 pinctrl: rockchip: fix leaked of_node references
The call to of_parse_phandle returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.

Detected by coccinelle with the following warnings:
./drivers/pinctrl/pinctrl-rockchip.c:3221:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 3196, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-rockchip.c:3223:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 3196, but without a corresponding object release within this function.

Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-gpio@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-23 09:24:46 +02:00
Thomas Gleixner
1ccea77e2a treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details you
  should have received a copy of the gnu general public license along
  with this program if not see http www gnu org licenses

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details [based]
  [from] [clk] [highbank] [c] you should have received a copy of the
  gnu general public license along with this program if not see http
  www gnu org licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 355 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 11:28:45 +02:00
Thomas Gleixner
a636cd6c42 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4
Based on 1 normalized pattern(s):

  licensed under gplv2 or later

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 118 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 11:28:40 +02:00
Geert Uytterhoeven
dd1f760bff pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macro
Get rid of the custom PORT_GP_PUP_27() macro by using the common
PORT_GP_CFG_27() macro instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
fbc5108d93 pinctrl: sh-pfc: Add PORT_GP_27 helper macro
This follows the style of the existing PORT_GP_X macros, and will be
used by a follow-up patch for the r8a7778 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
be1c072d66 pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-N SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
32ba9f222e pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-W and RZ/G2M SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
9141d4558f pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revisions ES2.x and later of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
0cbdf1b876 pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revision ES1.x of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
e7ad751628 pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}
Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit
definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and
IPSR7 registers, as these pin functionalities do not exist on R-Car
V3M.

Remove the definitions, and the corrresponding pins and groups.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
4d1816cd67 pinctrl: sh-pfc: Move PIN_NONE to shared header file
Several drivers have identical definitions for PIN_NONE.
Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h,
and convert all drivers over to use it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
f1074e7281 pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand
It is very common for a pin to support both pull-up and pull-down
functionality.  Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN.
This not only reduces typing, but also avoids the need for several line
breaks, and makes many overly long lines shorter, improving
readability.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
bd79c92039 pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant
There are two variants of the CPU_ALL_PORT() macro in use:
  1. A three-parameter variant, to be provided for SoCs with a linear
     GPIO pin space ("PORT style"),
  2. A two-parameter variant, to be provided for SoCs with 32-port GPIO
     banks ("GP port style").

Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
542ffc9e02 pinctrl: sh-pfc: Validate pin tables at runtime
Extend the run-time debug code with checks to ensure there are no
conflicting pin names, numbers, or enumeration values.

This helps catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
3dd5fd79f0 pinctrl: sh-pfc: Add check for empty pinmux groups/functions
The pinmux groups and functions arrays may contain two parts, to ease
supporting SoCs that expose pin subsets of other related SoCs.  Both
parts need to be declared with explicit sizes, which thus need to be
updated when adding support for more groups and functions.

If a size is too small, the compiler will detect this at build time
("excess elements in array initializer").
If a size is too large, this may go undetected (for pin groups), lead to
pin controller registration failures (for pin functions: "pinmux ops has
no name for functionN"), or crash the optional run-time debug code (for
pin groups).

Extend the run-time debug code with checks to detect this, to help
catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
80cde64f68 pinctrl: sh-pfc: Mark run-time debug code __init
All run-time debug code is called from sh_pfc_init(), which is __init.

Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
5f304f8c87 pinctrl: sh-pfc: Correct printk level of group reference warning
Improve wording while at it.

Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Thomas Gleixner
ec8f24b7fa treewide: Add SPDX license identifier - Makefile/Kconfig
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:46 +02:00
Thomas Gleixner
09c434b8a0 treewide: Add SPDX license identifier for more missed files
Add SPDX license identifiers to all files which:

 - Have no license information of any form

 - Have MODULE_LICENCE("GPL*") inside which was used in the initial
   scan/conversion to ignore the file

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21 10:50:45 +02:00
Kai-Heng Feng
670784fb4e pinctrl: intel: Clear interrupt status in mask/unmask callback
Commit a939bb57cd47 ("pinctrl: intel: implement gpio_irq_enable") was
added because clearing interrupt status bit is required to avoid
unexpected behavior.

Turns out the unmask callback also needs the fix, which can solve weird
IRQ triggering issues on I2C touchpad ELAN1200.

Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-05-20 15:04:25 +03:00
Andy Shevchenko
e58926e781 pinctrl: intel: Use GENMASK() consistently
Use GENMASK() macro for all definitions.
No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-05-20 15:04:25 +03:00
Linus Torvalds
ebcf5bb282 - Core Frameworks
- Document (kerneldoc) core mfd_add_devices() API
 
  - New Drivers
    - Add support for Altera SOCFPGA System Manager
    - Add support for Maxim MAX77650/77651 PMIC
    - Add support for Maxim MAX77663 PMIC
    - Add support for ST Multi-Function eXpander (STMFX)
 
  - New Device Support
    - Add support for LEDs to Intel Cherry Trail Whiskey Cove PMIC
    - Add support for RTC to SAMSUNG Electronics S2MPA01 PMIC
    - Add support for SAM9X60 to Atmel HLCDC (High-end LCD Controller)
    - Add support for USB X-Powers AXP 8xx PMICs
    - Add support for Integrated Sensor Hub (ISH) to ChromeOS EC
    - Add support for USB PD Logger to ChromeOS EC
    - Add support for AXP223 to X-Powers AXP series PMICs
    - Add support for Power Supply to X-Powers AXP 803 PMICs
    - Add support for Comet Lake to Intel Low Power Subsystem
    - Add support for Fingerprint MCU to ChromeOS EC
    - Add support for Touchpad MCU to ChromeOS EC
    - Move TI LM3532 support to LED
 
  - New Functionality
    - Add/extend DT support; max77650, max77620
    - Add support for power-off; max77620
    - Add support for clocking; syscon
    - Add support for host sleep event; cros_ec
 
  - Fix-ups
    - Trivial; Formatting, spelling, etc; Kconfig, sec-core, ab8500-debugfs
    - Remove unused functionality; rk808, da9063-*
    - SPDX conversion; da9063-*, atmel-*,
    - Adapt/add new register definitions; cs47l35-tables, cs47l90-tables, imx6q-iomuxc-gpr
    - Fix-up DT bindings; ti-lmu, cirrus,lochnagar
    - Simply obtaining driver data; ssbi, t7l66xb, tc6387xb, tc6393xb
 
  - Bug Fixes
    - Fix incorrect defined values; max77620, da9063
    - Fix device initialisation; twl6040
    - Reset device on init; intel-lpss
    - Fix build warnings when !OF; sun6i-prcm
    - Register OF match tables; tps65912-spi
    - Fix DMI matching; intel_quark_i2c_gpio
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAlzame0ACgkQUa+KL4f8
 d2GbBQ//bUoA+hcTo/ZUyQQGmE8axikZ6pacY+Y41pdzzLFoOM3IIz4NpdUF0fP2
 6r11zDiM2cL9CuMJl/AMiBv7fifowYykaBUEkkm8n2Cpj/bpLIm8eQy6jf14kqNR
 gj9sTy/feBcnZhqLLx9x9W9695nRTE4q3g+mDOj5sXRvZxqcPBaNgWkk5a8vtN9V
 yH2XkQSoK0EvvNWjl3pshp7HdKhX8k1xDZ2ghOi3Yk9JmFlg+wrWEKE4KQ7dDoUa
 SFXFReIwyleAw4Bc/demT1tSDiNgIPc9ZHtb67dUmDCQgpQqTK/h6WV1JeW1I0vh
 AM6n2hnogcbVcJdAHtwS5tR6nVahpUQ1V+XhYDyyHNmx6rqW5q2e3xRF75CT4wBZ
 NMIVaWNlih62Y196Exy+6CANHvJyxL6yRgvXkpfyaf9vYdXUrBRUujxn1PzrbkNJ
 kJwvZk5yHgg0n5SIV/D4CVy+RHP6uqe4oE4iXNWP5Um06OyVCieqMvoduyGQdLG/
 7Xrflc4EmeqTfWZrnW3ljh6sOBC+MQCfIKgRtvkPQ5EpcNU2VPXeNsAvIIHCpWHy
 HJY43WRP98DTNyP+/oBrsh56y8n+NwMBcWSmL4tv4cKmGx11bRvp35Mzy1ElPw6Y
 Zzttsw8Puz2EMmfGdcRwkZW0KWb5sAvJcImCkrjg/13QPHgcPgk=
 =dTSD
 -----END PGP SIGNATURE-----

Merge tag 'mfd-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "Core Framework:
   - Document (kerneldoc) core mfd_add_devices() API

  New Drivers:
   - Altera SOCFPGA System Manager
   - Maxim MAX77650/77651 PMIC
   - Maxim MAX77663 PMIC
   - ST Multi-Function eXpander (STMFX)

  New Device Support:
   - LEDs support in Intel Cherry Trail Whiskey Cove PMIC
   - RTC support in SAMSUNG Electronics S2MPA01 PMIC
   - SAM9X60 support in Atmel HLCDC (High-end LCD Controller)
   - USB X-Powers AXP 8xx PMICs
   - Integrated Sensor Hub (ISH) in ChromeOS EC
   - USB PD Logger in ChromeOS EC
   - AXP223 in X-Powers AXP series PMICs
   - Power Supply in X-Powers AXP 803 PMICs
   - Comet Lake in Intel Low Power Subsystem
   - Fingerprint MCU in ChromeOS EC
   - Touchpad MCU in ChromeOS EC
   - Move TI LM3532 support to LED

  New Functionality:
   - max77650, max77620: Add/extend DT support
   - max77620 power-off
   - syscon clocking
   - croc_ec host sleep event

  Fix-ups:
   - Trivial; Formatting, spelling, etc; Kconfig, sec-core, ab8500-debugfs
   - Remove unused functionality; rk808, da9063-*
   - SPDX conversion; da9063-*, atmel-*,
   - Adapt/add new register definitions; cs47l35-tables, cs47l90-tables, imx6q-iomuxc-gpr
   - Fix-up DT bindings; ti-lmu, cirrus,lochnagar
   - Simply obtaining driver data; ssbi, t7l66xb, tc6387xb, tc6393xb

  Bug Fixes:
   - Fix incorrect defined values; max77620, da9063
   - Fix device initialisation; twl6040
   - Reset device on init; intel-lpss
   - Fix build warnings when !OF; sun6i-prcm
   - Register OF match tables; tps65912-spi
   - Fix DMI matching; intel_quark_i2c_gpio"

* tag 'mfd-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (65 commits)
  mfd: Use dev_get_drvdata() directly
  mfd: cros_ec: Instantiate properly CrOS Touchpad MCU device
  mfd: cros_ec: Instantiate properly CrOS FP MCU device
  mfd: cros_ec: Update the EC feature codes
  mfd: intel-lpss: Add Intel Comet Lake PCI IDs
  mfd: lochnagar: Add links to binding docs for sound and hwmon
  mfd: ab8500-debugfs: Fix a typo ("deubgfs")
  mfd: imx6sx: Add MQS register definition for iomuxc gpr
  dt-bindings: mfd: LMU: Fix lm3632 dt binding example
  mfd: intel_quark_i2c_gpio: Adjust IOT2000 matching
  mfd: da9063: Fix OTP control register names to match datasheets for DA9063/63L
  mfd: tps65912-spi: Add missing of table registration
  mfd: axp20x: Add USB power supply mfd cell to AXP803
  mfd: sun6i-prcm: Fix build warning for non-OF configurations
  mfd: intel-lpss: Set the device in reset state when init
  platform/chrome: Add support for v1 of host sleep event
  mfd: cros_ec: Add host_sleep_event_v1 command
  mfd: cros_ec: Instantiate the CrOS USB PD logger driver
  mfd: cs47l90: Make DAC_AEC_CONTROL_2 readable
  mfd: cs47l35: Make DAC_AEC_CONTROL_2 readable
  ...
2019-05-14 10:39:08 -07:00
Lee Jones
d17ed797b8 pinctrl: stmfx: Fix 'warn: bitwise AND condition is false here'
drivers/pinctrl/pinctrl-stmfx.c:441 stmfx_pinctrl_irq_set_type() warn: bitwise AND condition is false here

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-13 08:28:26 +01:00
Lee Jones
28a853860f pinctrl: stmfx: Fix 'warn: unsigned <VAR> is never less than zero'
smatch warnings:
drivers/pinctrl/pinctrl-stmfx.c:225 stmfx_pinconf_get() warn: unsigned 'dir' is never less than zero.
drivers/pinctrl/pinctrl-stmfx.c:228 stmfx_pinconf_get() warn: unsigned 'type' is never less than zero.
drivers/pinctrl/pinctrl-stmfx.c:231 stmfx_pinconf_get() warn: unsigned 'pupd' is never less than zero.

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-13 08:28:20 +01:00
Linus Torvalds
8148c17b17 This is the bulk of the GPIO changes for the v5.2 kernel cycle:
Core changes:
 - The gpiolib MMIO driver has been enhanced to handle two direction
   registers, i.e. one register to set lines as input and one register
   to set lines as output. It turns out some silicon engineer thinks
   the ability to configure a line as input and output at the same
   time makes sense, this can be debated but includes a lot of analog
   electronics reasoning, and the registers are there and need to
   be handled consistently. Unsurprisingly, we enforce the lines to
   be either inputs or outputs in such schemes.
 - Send in the proper argument value to .set_config() dispatched to
   the pin control subsystem. Nobody used it before, now someone
   does, so fix it to work as expected.
 - The ACPI gpiolib portions can now handle pin bias setting (pull up
   or pull down). This has been in the ACPI spec for years and we
   finally have it properly integrated with Linux GPIOs. It was based
   on an observation from Andy Schevchenko that Thomas Petazzoni's
   changes to the core for biasing the PCA950x GPIO expander actually
   happen to fit hand-in-glove with what the ACPI core needed.
   Such nice synergies happen sometimes.
 
 New drivers:
 - A new driver for the Mellanox BlueField GPIO controller. This is
   using 64bit MMIO registers and can configure lines as inputs
   and outputs at the same time and after improving the MMIO library
   we handle it just fine. Interesting.
 - A new IXP4xx proper gpiochip driver with hierarchical interrupts
   should be coming in from the ARM SoC tree as well.
 
 Driver enhancements:
 - The PCA053x driver handles the CAT9554 GPIO expander.
 - The PCA053x driver handles the NXP PCAL6416 GPIO expander.
 - Wake-up support on PCA053x GPIO lines.
 - OMAP now does a nice asynchronous IRQ handling on wake-ups by
   letting everything wake up on edges, and this makes runtime PM
   work as expected too.
 
 Misc:
 - Several cleanups such as devres fixes.
 - Get rid of some languager comstructs that cause problems when
   compiling with LLVMs clang.
 - Documentation review and update.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJc1olZAAoJEEEQszewGV1zEU4P/RmTf3hG8xmNPS3MDTmR6gAy
 /YJOXjXBf3CD/dmEAyyaNLnUQismrtRNvHSoEGbno7gkU+htzp9UfUJkj6+HIXs2
 RpF+Hi78HzZNDxGWuBLu6OZolpmBtx+sRKOhHk/XfNS45qd1FgXWDuulzsYa9Xsr
 hYMXdtdv9wY/vcc68q1rtKAbzlu5ZNCa3Zj1iNOr/XQt3Nl2BW66hGLgjK4mOvgx
 fJy4rFXuDIMfDvo69U1Opz2b39sfE7XMhfZS/MOgg4yEV9zGRgDoI1tyMcTqGb8Q
 8LQbp5dXkP+3dJQB8tgbu3Vk4WC1Rd/pmIli5sMgsk0HYQ6XegfT6HJKozSmwN9r
 0s8jKlrocWZvdPo1aJwQgtRS56t2rFWcrcRye8bLqxkkW5cYIq9CwkE8USwB31Kv
 PFpoOwRuCtj0gkCxf7WIEcC5NAkYPow3K1KPdk3E0Si6I3pj0NqqlaAD0JAlkC2V
 aPq3xbTuFCAdmcADEt2Z+dUJ7WIs5Y9oQgosMAx+A2AD4K3QDBMu3pZsT6SCu4XZ
 mK0eWJi9/CvOj/s7bA0BEJVxQA+p8KYsNRBOULg/8aAOqGcLnSydQjqrxDTE8YrL
 xmmRG7i7ht0B9CchZuIB5hqdvjbCgvcVa5OnCUDfLxE0GdCx8iJ9y9OrsMXbabYq
 8FcPDo1N38cTYLnLqvKI
 =rhto
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull gpio updates from Linus Walleij:
 "This is the bulk of the GPIO changes for the v5.2 kernel cycle. A bit
  later than usual because I was ironing out my own mistakes. I'm
  holding some stuff back for the next kernel as a result, and this
  should be a healthy and well tested batch.

  Core changes:

   - The gpiolib MMIO driver has been enhanced to handle two direction
     registers, i.e. one register to set lines as input and one register
     to set lines as output. It turns out some silicon engineer thinks
     the ability to configure a line as input and output at the same
     time makes sense, this can be debated but includes a lot of analog
     electronics reasoning, and the registers are there and need to be
     handled consistently. Unsurprisingly, we enforce the lines to be
     either inputs or outputs in such schemes.

   - Send in the proper argument value to .set_config() dispatched to
     the pin control subsystem. Nobody used it before, now someone does,
     so fix it to work as expected.

   - The ACPI gpiolib portions can now handle pin bias setting (pull up
     or pull down). This has been in the ACPI spec for years and we
     finally have it properly integrated with Linux GPIOs. It was based
     on an observation from Andy Schevchenko that Thomas Petazzoni's
     changes to the core for biasing the PCA950x GPIO expander actually
     happen to fit hand-in-glove with what the ACPI core needed. Such
     nice synergies happen sometimes.

  New drivers:

   - A new driver for the Mellanox BlueField GPIO controller. This is
     using 64bit MMIO registers and can configure lines as inputs and
     outputs at the same time and after improving the MMIO library we
     handle it just fine. Interesting.

   - A new IXP4xx proper gpiochip driver with hierarchical interrupts
     should be coming in from the ARM SoC tree as well.

  Driver enhancements:

   - The PCA053x driver handles the CAT9554 GPIO expander.

   - The PCA053x driver handles the NXP PCAL6416 GPIO expander.

   - Wake-up support on PCA053x GPIO lines.

   - OMAP now does a nice asynchronous IRQ handling on wake-ups by
     letting everything wake up on edges, and this makes runtime PM work
     as expected too.

  Misc:

   - Several cleanups such as devres fixes.

   - Get rid of some languager comstructs that cause problems when
     compiling with LLVMs clang.

   - Documentation review and update"

* tag 'gpio-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (85 commits)
  gpio: Update documentation
  docs: gpio: convert docs to ReST and rename to *.rst
  gpio: sch: Remove write-only core_base
  gpio: pxa: Make two symbols static
  gpiolib: acpi: Respect pin bias setting
  gpiolib: acpi: Add acpi_gpio_update_gpiod_lookup_flags() helper
  gpiolib: acpi: Set pin value, based on bias, more accurately
  gpiolib: acpi: Change type of dflags
  gpiolib: Introduce GPIO_LOOKUP_FLAGS_DEFAULT
  gpiolib: Make use of enum gpio_lookup_flags consistent
  gpiolib: Indent entry values of enum gpio_lookup_flags
  gpio: pca953x: add support for pca6416
  dt-bindings: gpio: pca953x: document the nxp,pca6416
  gpio: pca953x: add pcal6416 to the of_device_id table
  gpio: gpio-omap: Remove conditional pm_runtime handling for GPIO interrupts
  gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup
  tracing: stop making gpio tracing configurable
  gpio: pca953x: Configure wake-up path when wake-up is enabled
  gpio: of: Optimize quirk checks
  gpio: mmio: Drop bgpio_dir_inverted
  ...
2019-05-11 10:54:43 -04:00
Amelie Delaunay
9af2de7657 pinctrl: Kconfig: Fix STMFX GPIO expander Pinctrl/GPIO driver dependencies
module_i2c_driver and pinconf_generic_dt_node_to_map_pin are undeclared
if CONFIG_I2C and CONFIG_OF are not enabled.

Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-10 16:09:56 +01:00
Amelie Delaunay
1490d9f841 pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on generic pin config interface to configure the GPIOs.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-10 08:21:31 +01:00
Jan Kundrát
e0e31695b5 pinctrl: mcp23s08: Do not complain about unsupported params
It is expected that some of these operations won't work on each and
every HW. Previously, even a simple `cat
/sys/kernel/debug/pinctrl/spi1.1/pinconf-pins` caused excessive dmesg
output.

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Phil Reid <preid@electromag.com.au>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-07 11:47:14 +02:00
Linus Walleij
48f6ae0d75 intel-pinctrl for v5.2-1
Non-critical fixes for Intel Baytrail and Intel Cedarfork.
 Couple of fixes for all pinctrl-intel based drivers with regard to
 IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose
 and restore ownership of pins to prevent IRQ masking side effect.
 
 The following is an automated git shortlog grouped by driver:
 
 baytrail:
  -  Fix potential NULL pointer dereference
 
 cedarfork:
  -  Update pin names according to v1.13c
 
 intel:
  -  Increase readability of intel_gpio_update_pad_mode()
  -  Retain HOSTSW_OWN for requested gpio pin
  -  move gpio suspend/resume to noirq phase
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAlzGyScACgkQb7wzTHR8
 rCjR6w/+OHPEzftvLzlgdOQ8sopxLt/LXoDcDcIufT83VTYdz+QVi0rMPj0fBkDA
 OWCvvdehJS0VkyOJPw91z8GAxvtjOkqqGoQ8n4V+vzLphjkmNu9R6d243mMH7nCl
 Trda4MLkmdDtTCQ/iF+tZmzuimKHTLpQfy1Bld0mcNcxdfMLqqe+BD7OtAwIfKr6
 LooTVtoqTx+GobmdSWBTaa0+D+nYVsbMwBW/cd+8j/f2MnZ3czhApygCwilAZdU5
 etUm2SmCJf2spdkcoxDJ10tih8NH8+dJgmIjU2LTn98pqaSllkT9egfv5tpUq+ag
 /sRnI1yxi9nmijXMbXl03XUynKxDIlNXcm9hza5EZoLDMAOixwiUSX8ypLTZtSqZ
 mfC37FMCUKomMvcUtKeya0v8uTJRTLEszS4LuL6q+fopm/sV6nicP3/WIfsAbBwf
 Kzk8QNZL9CaSRyOxXmnrZvG/CkBYIjVZfJloX7Ia5fZYJBmJ/3U9qfvUqDDJQmn7
 EHmhROXRckAjtABa48CyV7BnTQeuhZP6cDFRKZ4AiqHHC8mhJVsSfPq7OUYnET8H
 V0qix20b5315+VY7I1nYFU7BCJ+gLdef0Hg1znTZFf8Z1poG18feesjujZ3/x2dg
 fDcS+Il3Z8JXaZT1ljgi+cffzAgWUNpkFn15iBqP3uP6MBbshLU=
 =tsfB
 -----END PGP SIGNATURE-----

Merge tag 'intel-pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.2-1

Non-critical fixes for Intel Baytrail and Intel Cedarfork.
Couple of fixes for all pinctrl-intel based drivers with regard to
IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose
and restore ownership of pins to prevent IRQ masking side effect.

The following is an automated git shortlog grouped by driver:

baytrail:
 -  Fix potential NULL pointer dereference

cedarfork:
 -  Update pin names according to v1.13c

intel:
 -  Increase readability of intel_gpio_update_pad_mode()
 -  Retain HOSTSW_OWN for requested gpio pin
 -  move gpio suspend/resume to noirq phase
2019-05-03 07:53:33 +01:00
Manivannan Sadhasivam
8293b3c6da pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
Make the BM1880 SoC pinctrl driver depend on COMPILE_TEST to get compiler
test coverage and also select this driver by default for ARCH_BITMAIN
platform.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03 07:53:13 +01:00
Manivannan Sadhasivam
8f3f024696 pinctrl: Add pinctrl support for BM1880 SoC
Add pinctrl support for Bitmain BM1880 SoC. The driver only handles
pinmuxing as the SoC is not capable of handling pinconf.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03 07:53:13 +01:00
Fabien Dessenne
d86f4d71e4 pinctrl: stm32: check irq controller availability at probe
It is not guaranteed that the IRQ controller driver is probed before
the pin controller driver gets probed.
Considering this, check for the irq domain availability during probe
and return EPROBE_DEFER if needed.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03 07:53:13 +01:00
Fabien Parent
264667112e pinctrl: mediatek: Add MT8516 Pinctrl driver
This commit adds the pinctrl driver for the MediaTek's MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03 07:53:13 +01:00
Wen Yang
02d15f0d80 pinctrl: zte: fix leaked of_node references
The call to of_parse_phandle returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.

Detected by coccinelle with the following warnings:
./drivers/pinctrl/zte/pinctrl-zx.c:415:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:422:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:436:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:444:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:448:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.

Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-05-03 07:53:13 +01:00
Andy Shevchenko
5f61d9517f pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
We better to use usual pattern for read-modify-update,
than doing some operations in definition block.

No functional change.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-28 20:19:06 +03:00
Chris Chiu
a0a5f7661e pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
The touchpad of the ASUS laptops E403NA, X540NA, X541NA are not
responsive after suspend/resume. The following error message
shows after resume.
 i2c_hid i2c-ELAN1200:00: failed to reset device.

On these laptops, the touchpad interrupt is connected via a GPIO
pin which is controlled by Intel pinctrl. After system resumes,
the GPIO is in ACPI mode and no longer works as an IRQ.

This commit saves the HOSTSW_OWN value during suspend, make sure
the HOSTSW_OWN mode remains the same after resume.

Signed-off-by: Chris Chiu <chiu@endlessm.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-28 20:10:06 +03:00
Wen Yang
44a4455ac2 pinctrl: pistachio: fix leaked of_node references
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.

Detected by coccinelle with the following warnings:
./drivers/pinctrl/pinctrl-pistachio.c:1422:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1360, but without a corresponding object release within this function.

Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 12:34:11 +02:00
Ondrej Jirman
cc62383fce pinctrl: sunxi: Support I/O bias voltage setting on H6
H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.

Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).

This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:

  commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")

Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 12:31:42 +02:00
Ondrej Jirman
f727534572 pinctrl: sunxi: Prepare for alternative bias voltage setting methods
H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 12:29:21 +02:00
Wen Yang
483d70d73b pinctrl: st: fix leaked of_node references
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.

Detected by coccinelle with the following warnings:
./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.

Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org (open list)
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 11:01:17 +02:00