12 Commits

Author SHA1 Message Date
Chen-Yu Tsai
d2aa6f5400 ARM: dts: sun9i: Add mmc module clock nodes for A80
The mmc module clocks are A80 specific module 0 (storage) type clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21 09:59:15 +01:00
Maxime Ripard
19882b84d7 ARM: sunxi: DT: Convert the DTs to use the GIC headers
The GIC requires some extra opaque arguments to set the IRQ type and flags.

Convert the DTs to using the common defines.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21 09:58:57 +01:00
Maxime Ripard
092a0c3b18 ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodes
The pinctrl nodes require some extra opaque arguments for the pull up and drive
strength values.

Introduce a new header file and convert the device trees to replace these
opaque numbers by defines.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21 09:58:57 +01:00
Maxime Ripard
7145570159 ARM: sunxi: DT: Convert to device tree includes
Prepare the device trees to use the C preprocessor.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21 09:58:55 +01:00
Chen-Yu Tsai
2a950b2ca0 ARM: dts: sun9i: Add uart4 pinmux setting for A80 SoC
uart4 only has one possible pinmux setting on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31 09:25:41 +01:00
Chen-Yu Tsai
6657a05872 ARM: dts: sun9i: Add i2c3 pinmux setting for A80 SoC
i2c3 has only one possible pinmux setting on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31 09:25:11 +01:00
Chen-Yu Tsai
e4aa753a72 ARM: dts: sun9i: Add i2c controller nodes to a80 dtsi
The A80 has 5 i2c controllers in the main processor block.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31 09:25:01 +01:00
Maxime Ripard
888366fa17 ARM: sun9i: optimus: Set UART0 muxing
Enable the UART0 muxing, as set up by the bootloader.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-30 16:36:49 +01:00
Maxime Ripard
43d024d36a ARM: sun9i: Enable the A80 pinctrl driver
The A80 pinctrl driver is just as usual our pinctrl/gpio/external interrupt
controller.

Nothing really out of the extraordinary here...

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-30 16:36:45 +01:00
Maxime Ripard
136d18a84b ARM: sunxi: Fix GPLv2 wording
During the GPL to GPL/X11 licensing migration, the GPL notice introduced
mentionned the device trees as a library, which is not really accurate. It
began to spread by copy and paste. Fix all these library mentions to reflect
the file that it's actually just a file.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-27 23:04:41 +01:00
Chen-Yu Tsai
ac399a971d ARM: dts: sun9i: Add basic clocks and reset controls
Now that we have driver support for the basic clocks, add them to the
dtsi and update existing peripherals. Also add reset controls to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:50:39 +02:00
Chen-Yu Tsai
4ab328f06e ARM: dts: sunxi: Add Allwinner A80 dtsi
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core
PowerVR G6230 GPU.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
2014-10-20 14:52:12 +02:00