1145 Commits

Author SHA1 Message Date
Linus Torvalds
8395d932d2 Devicetree updates for v6.3:
DT core:
 - Add node lifecycle unit tests
 
 - Add of_property_present() helper aligned with fwnode API
 
 - Print more information on reserved regions on boot
 
 - Update dtc to upstream v1.6.1-66-gabbd523bae6e
 
 - Use strscpy() to instead of strncpy() in DT core
 
 - Add option for schema validation on %.dtb targets
 
 Bindings:
 - Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
 
 - Rework external memory controller/bus bindings to properly support
   controller specific child node properties
 
 - Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip RK3399
   PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT schema format
 
 - Add RiscV SBI PMU event mapping binding
 
 - Add missing contraints on Arm SCMI child node allowed properties
 
 - Add a bunch of missing Socionext UniPhier glue block bindings and
   example fixes
 
 - Various fixes for duplicate or conflicting type definitions on DT
   properties
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Merge tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Add node lifecycle unit tests

   - Add of_property_present() helper aligned with fwnode API

   - Print more information on reserved regions on boot

   - Update dtc to upstream v1.6.1-66-gabbd523bae6e

   - Use strscpy() to instead of strncpy() in DT core

   - Add option for schema validation on %.dtb targets

  Bindings:

   - Add/fix support for listing multiple patterns in DT_SCHEMA_FILES

   - Rework external memory controller/bus bindings to properly support
     controller specific child node properties

   - Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip
     RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT
     schema format

   - Add RiscV SBI PMU event mapping binding

   - Add missing contraints on Arm SCMI child node allowed properties

   - Add a bunch of missing Socionext UniPhier glue block bindings and
     example fixes

   - Various fixes for duplicate or conflicting type definitions on DT
     properties"

* tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits)
  dt-bindings: regulator: Add mps,mpq7932 power-management IC
  of: dynamic: Fix spelling mistake "kojbect" -> "kobject"
  dt-bindings: drop Sagar Kadam from SiFive binding maintainership
  dt-bindings: sram: qcom,imem: document sm8450
  dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema
  dt-bindings: arm: Add Cortex-A715 and X3
  of: dynamic: add lifecycle docbook info to node creation functions
  of: add consistency check to of_node_release()
  of: do not use "%pOF" printk format on node with refcount of zero
  of: unittest: add node lifecycle tests
  of: update kconfig unittest help
  of: add processing of EXPECT_NOT to of_unittest_expect
  of: prepare to add processing of EXPECT_NOT to of_unittest_expect
  of: Use preferred of_property_read_* functions
  of: Use of_property_present() helper
  of: Add of_property_present() helper
  of: reserved_mem: Use proper binary prefix
  dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES
  of: reserved-mem: print out reserved-mem details during boot
  dt-bindings: serial: restrict possible child node names
  ...
2023-02-24 13:31:53 -08:00
Jianlong Huang
716129d3b7 dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230209143702.44408-3-hal.feng@starfivetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-10 23:44:07 +01:00
Jianlong Huang
d6e0a66009 dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230209143702.44408-2-hal.feng@starfivetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-10 23:44:07 +01:00
Linus Walleij
1ec033f00c Qualcomm pinctrl Devicetree bindings changes for v6.3, part two
Several minor cleanups and fixes on Qualcomm pin controller Devicetree
 bindings - add missing input-disable, correct GPIO pin name patterns in
 bindings, correct number of GPIOs in gpio-ranges property.
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Merge tag 'qcom-pinctrl-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel

Qualcomm pinctrl Devicetree bindings changes for v6.3, part two

Several minor cleanups and fixes on Qualcomm pin controller Devicetree
bindings - add missing input-disable, correct GPIO pin name patterns in
bindings, correct number of GPIOs in gpio-ranges property.
2023-02-08 16:07:59 +01:00
Daniel Golle
d4059de433 dt-bindings: pinctrl: add bindings for MT7981 SoC
Add bindings for the MT7981 pinctrl driver. As MT7981 has most features
in common with MT7986 (but has a different layout in terms on pinctrl
and clocks), the existing mediatek,mt7986-pinctrl.yaml was used as an
example to create a similar document covering MT7981.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/3f0fd0becc338eef66caeb7244c3c432b8d1ef7a.1674693008.git.daniel@makrotopia.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-07 15:44:51 +01:00
Johan Jonker
9421655de8 dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated
Mark gpio sub nodes of pinctrl as deprecated.
Gpio nodes are now placed in the root of the device tree.
The relation to pinctrl is now described with the
"gpio-ranges" property.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/137b56f0-8e86-f705-4ba7-d5dfe3c0b477@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-07 15:44:51 +01:00
Kathiravan T
2e78514377 dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
Add device tree bindings for IPQ5332 TLMM block.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230206071217.29313-2-quic_kathirav@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-06 12:23:12 +01:00
Krzysztof Kozlowski
315dffb843 dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
Narrow the pattern of possible GPIO names for pin controllers:
 - SC7280 LPASS: GPIOs 0-14
 - SM8250 LPASS: GPIOs 0-13
 - SM8450 LPASS: GPIOs 0-22
 - SC8280XP LPASS: GPIOs 0-18

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230203164854.390080-1-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-2-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-3-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-06 12:17:55 +01:00
Krzysztof Kozlowski
268e97ccc3 dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS
Add bidings for pin controller in Low Power Audio SubSystem (LPASS).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230203174645.597053-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-06 12:15:51 +01:00
Krzysztof Kozlowski
6f4e10ffa8 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples
Correct the number of GPIOs in gpio-ranges to match reality.

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:15:06 +01:00
Krzysztof Kozlowski
174668bf5f dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs
The MSM8994 TLMM pin controller has GPIOs 0-145, so narrow the pattern
and reduce sizes of arrays with pins.

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:15:02 +01:00
Krzysztof Kozlowski
5c7069712c dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern
The SDX55 TLMM pin controller has GPIOs 0-107, so narrow the pattern.

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:58 +01:00
Krzysztof Kozlowski
913137a1cd dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern
The MSM8953 TLMM pin controller has GPIOs 0-141, so narrow the pattern.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230202104452.299048-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:53 +01:00
Krzysztof Kozlowski
a51c1f0244 dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example
The SM6375 TLMM pin controller has GPIOs 0-155, so narrow the pattern
and gpio-ranges in the example.

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:51 +01:00
Krzysztof Kozlowski
87b93dd1fb dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example
The MSM8909 TLMM pin controller has GPIOs 0-112, so narrow the pattern
and gpio-ranges in the example.

Fixes: c249ec7ba1b1 ("dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm")
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230202104452.299048-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:48 +01:00
Krzysztof Kozlowski
792349083a dt-bindings: pinctrl: qcom,msm8226: correct GPIO name pattern
The MSM8226 TLMM pin controller has GPIOs 0-116, so correct the pattern
to bring back missing 107-109.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230202104452.299048-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:45 +01:00
Krzysztof Kozlowski
91d04c759c dt-bindings: pinctrl: qcom,sm8350: add input-disable
The SM8350 HDK8350 board uses input-disable property, so allow it:

  sm8350-hdk.dtb: pinctrl@f100000: lt9611-state: 'oneOf' conditional failed, one must be fixed:
    ...
    'input-disable' does not match any of the regexes: 'pinctrl-[0-9]+'

Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230201154321.276419-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-03 08:14:18 +01:00
Bartosz Golaszewski
9a2aaee23c dt-bindings: pinctrl: describe sa8775p-tlmm
Add DT bindings for the TLMM controller on sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230201150011.200613-2-brgl@bgdev.pl
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-02-01 23:44:49 +01:00
Linus Walleij
9da134e270 Qualcomm pinctrl Devicetree bindings changes for v6.3
Set of cleanups and fixes for Qualcomm pin controller bindings, to match
 existing DTS and correct the schema.
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Merge tag 'qcom-pinctrl-6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel

Qualcomm pinctrl Devicetree bindings changes for v6.3

Set of cleanups and fixes for Qualcomm pin controller bindings, to match
existing DTS and correct the schema.
2023-01-27 14:02:01 +01:00
Rob Herring
6c488fbb1d dt-bindings: pinctrl: mediatek: Fix child node name patterns
The child node name patterns in Mediatek pinctrl bindings don't match
reality. I don't know where '-[0-9]+$' came from, but I don't see any nodes
with a matching pattern. Also, patterns such as 'pins' or 'mux' are
ambiguous because any prefix or suffix is allowed. If that's desired, it
should be explicit.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230120020536.3229300-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-27 13:31:34 +01:00
Bernhard Rosenkränzer
b2ea28b885 dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
Add devicetree bindings for Mediatek MT8365 pinctrl driver.

Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230125143503.1015424-5-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-26 14:52:48 +01:00
Rob Herring
5b8c304c94 dt-bindings: pinctrl: qcom,pmic-mpp: Rename "mpp" child node names to "-pins$"
Just 'mpp' is a bit ambiguous for a pattern as it allows any prefix or
suffix. Change the node name pattern to "-pins$" to align with other
Qualcomm pinctrl bindings.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230120165103.1278852-1-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-20 18:43:06 +01:00
Arınç ÜNAL
844bca6092 dt-bindings: pinctrl: rt3883: add proper function muxing binding
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-7-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-16 14:56:46 +01:00
Arınç ÜNAL
d648fd64e1 dt-bindings: pinctrl: rt305x: add proper function muxing binding
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-6-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-16 14:56:46 +01:00
Arınç ÜNAL
b4ac843958 dt-bindings: pinctrl: rt2880: add proper function muxing binding
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-5-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-16 14:56:46 +01:00
Arınç ÜNAL
0c9a567651 dt-bindings: pinctrl: mt7621: add proper function muxing binding
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-4-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-16 14:56:46 +01:00
Arınç ÜNAL
4e5410668a dt-bindings: pinctrl: mt7620: add proper function muxing binding
Not every function can be muxed to a group. Add proper binding which
documents which function can be muxed to a group or set of groups.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20221231160849.40544-3-arinc.unal@arinc9.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-16 14:56:46 +01:00
Krzysztof Kozlowski
12a18bb74f dt-bindings: pinctrl: qcom: allow nine interrupts on SM6350
Almost all Qualcomm SoC Top Level Mode Multiplexers come with only
summary interrupt.  SM6350 is different because downstream and upstream
DTS have nine of the interrupts.  Allow such variation.

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:52 +01:00
Krzysztof Kozlowski
45277153d4 dt-bindings: pinctrl: qcom,sm8350-tlmm: correct pins pattern
SM8350 TLMM pin controller has GPIOs 0-202.

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:46 +01:00
Krzysztof Kozlowski
72283404c2 dt-bindings: pinctrl: qcom,sm6350-tlmm: correct pins pattern
SM6350 TLMM pin controller has GPIOs 0-155.

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:43 +01:00
Krzysztof Kozlowski
86a8754b08 dt-bindings: pinctrl: qcom,sm8350-tlmm: add gpio-line-names
Allow gpio-line-names property (quite commonly used) and constrain
gpio-reserved-ranges:

  sm8350-sony-xperia-sagami-pdx215.dtb: pinctrl@f100000: 'gpio-line-names' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+'

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:41 +01:00
Krzysztof Kozlowski
d3431ec2f7 dt-bindings: pinctrl: qcom,sm6350-tlmm: add gpio-line-names
Allow gpio-line-names property (quite commonly used) and constrain
gpio-reserved-ranges.

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:38 +01:00
Krzysztof Kozlowski
a880fafbba dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: add input-enable and bias-bus-hold
Allow bias-bus-hold and input-enable properties (already used in
SC8280XP LPASS LPI nodes):

  sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
    'pins' is a required property
    'function' is a required property
    'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
    'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'

Link: https://lore.kernel.org/r/20221230135645.56401-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:21 +01:00
Krzysztof Kozlowski
3c90b1ba8c dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: correct pins pattern
SC8280XP LPASS LPI pin controller has GPIO 0-18:

  sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
    'pins' is a required property
    'function' is a required property
    'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
    'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'
    'gpio2' does not match '^gpio([0-1]|1[0-8])$'

Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings")
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 11:47:06 +01:00
Krzysztof Kozlowski
9eef05e606 dt-bindings: pinctrl: qcom,sdm845-pinctrl: add GPIO hogs
Allow GPIO hogs in pin controller node.  qcom/sdm845-cheza.dtsi already
uses it.

Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221121081221.30745-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13 10:03:35 +01:00
Krzysztof Kozlowski
697550668b dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: add input-enable and bias-bus-hold
Allow bias-bus-hold and input-enable properties (already used in SM8450):

  sm8450-qrd.dtb: pinctrl@3440000: dmic02-default-state: 'oneOf' conditional failed, one must be fixed:
    'pins' is a required property
    'function' is a required property
    'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
    'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+'

Compact the properties which are just set to true for readability.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221222161420.172824-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-10 09:06:49 +01:00
Krzysztof Kozlowski
3ecc01c5e0 dt-bindings: pinctrl: qcom,sm8450-tlmm: correct gpio-line-names size
The SM8450 has GPIOs from 0 to 209, so 210 in total:

  sm8450-sony-xperia-nagara-pdx223.dtb: pinctrl@f100000: gpio-line-names:
    ['NC', 'NC', 'NC', 'NC', 'WLC_I2C_SDA', 'WLC_I2C_SCL', ...
     'APPS_I2C_0_SDA', 'APPS_I2C_0_SCL', 'CCI_I2C3_SDA', 'CCI_I2C3_SCL'] is too long

Fixes: 9779ed30f92c ("dt-bindings: pinctrl: qcom,sm8450-pinctrl: add gpio-line-names")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221223132226.81340-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-10 09:05:51 +01:00
Matti Lehtimäki
ef6c2d8566 dt-bindings: pinctrl: msm8226: Add General Purpose clocks
Document the general purpose clock functions that are found on MSM8226.

Signed-off-by: Matti Lehtimäki <matti.lehtimaki@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230106114403.275865-2-matti.lehtimaki@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-10 08:56:33 +01:00
Peng Fan
f4720b845b dt-bindings: pinctrl: imx8m: Integrate duplicated i.MX 8M schemas
The i.MX8MM/N/P/Q IOMUXC schemas are basically the same, it does not to
have four schemas for almost the same binding.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230104021430.3503497-1-peng.fan@oss.nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-10 08:53:46 +01:00
Neil Armstrong
b754f00dd9 dt-bindings: pinctrl: qcom,pmic-gpio: document pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550 & pmr735d
Document compatible, pin count & pin names for pm8550, pm8550b, pm8550ve,
pm8550vs, pmk8550 & pmr735d SPMI GPIO controllers.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221114-narmstrong-sm8550-upstream-spmi-v2-2-b839bf2d558a@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-09 15:17:24 +01:00
Abel Vesa
15dfa161cc dt-bindings: pinctrl: qcom: Add SM8550 pinctrl
Add device tree binding Documentation details for Qualcomm SM8550
TLMM device

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221230203637.2539900-2-abel.vesa@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-01-09 14:19:50 +01:00
Melody Olvera
2daa14811e dt-bindings: pinctrl: qcom: Add QDU1000 and QRU1000 pinctrl
Add device tree bindings for QDU1000 and QRU1000 TLMM devices.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221216230852.21691-2-quic_molvera@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-29 02:34:53 +01:00
Biju Das
84f0b1ea2a dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221215213206.56666-2-biju.das.jz@bp.renesas.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-29 02:10:36 +01:00
Kunihiko Hayashi
3fa1306d6a dt-bindings: pinctrl: Fix node descriptions in uniphier-pinctrl example
Drop parent node of the pinctrl as it is not directly necessary, and
add more examples, that is "groups", "function", and a child node to set
pin attributes, to express this pinctrl node in detail.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221213082449.2721-4-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
2022-12-26 16:09:29 -06:00
Krzysztof Kozlowski
3367934dd3 dt-bindings: drop redundant part of title (manual)
The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding" or a "schema", but instead just describe
the hardware.

Manual updates to various binding titles, including capitalizing them.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # opp
Link: https://lore.kernel.org/r/20221216163815.522628-10-krzysztof.kozlowski@linaro.org
[robh: add trivial-devices.yaml and net/can/microchip,mcp251xfd.yaml]
Signed-off-by: Rob Herring <robh@kernel.org>
2022-12-16 12:51:43 -06:00
Krzysztof Kozlowski
84e85359f4 dt-bindings: drop redundant part of title (end, part three)
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.

Drop trailing "bindings" in various forms (also with trailing full
stop):

  find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
    -not -name 'trivial-devices.yaml' \
    -exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
2022-12-16 11:41:49 -06:00
Krzysztof Kozlowski
a612130ca1 dt-bindings: drop redundant part of title (end)
The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding", but instead just describe the hardware.

Drop trailing "Devicetree bindings" in various forms (also with
trailing full stop):

  find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
    -not -name 'trivial-devices.yaml' \
    -exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[tT]ree [bB]indings\?\.\?$/title: \1/' {} \;

  find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
    -not -name 'trivial-devices.yaml' \
    -exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[nN]ode [bB]indings\?\.\?$/title: \1/' {} \;

  find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
    -not -name 'trivial-devices.yaml' \
    -exec sed -i -e 's/^title: \(.*\) [dD][tT] [bB]indings\?\.\?$/title: \1/' {} \;

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # IIO
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Link: https://lore.kernel.org/r/20221216163815.522628-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
2022-12-16 11:41:49 -06:00
Linus Torvalds
361c89a0da Pin control changes for the v6.2 kernel cycle:
Core changes:
 
 - Minor but nice and important documentation clean-ups.
 
 New drivers:
 
 - New subdriver for the Qualcomm SDM670 SoC.
 
 - New subdriver for the Intel Moorefield SoC.
 
 - New trivial support for the NXP Freescale i.MXRT1170 SoC.
 
 Other changes and improvements
 
 - A major clean-up of the Qualcomm pin control device tree bindings
   by Krzysztof.
 
 - A major header clean-up by Andy.
 
 - Some immutable irqchip clean-up for the Actions Semiconductor
   and Nuvoton drivers.
 
 - GPIO helpers for The Cypress cy8c95x0 driver.
 
 - Bias handling in the Mediatek MT7986 driver.
 
 - Remove the unused pins-are-numbered concept that never flew.
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Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "The two large chunks is the header clean-up from Andy and the Qualcomm
  DT bindings clean-up from Krzysztof. Each which could give rise to
  conflicts, but I haven't seen any.

  The YAML conversions happening around the device tree is the biggest
  item in the series and is the result of Rob Herrings ambition to
  autovalidate these trees against strict schemas and it is paying off
  in lots of bugs found and ever prettier device trees. Sooner or later
  the transition will be complete, Krzysztof is fixing up all of the
  Qualcomm stuff, which is pretty voluminous.

  Core changes:

   - minor but nice and important documentation clean-ups

  New drivers:

   - subdriver for the Qualcomm SDM670 SoC

   - subdriver for the Intel Moorefield SoC

   - trivial support for the NXP Freescale i.MXRT1170 SoC

  Other changes and improvements

   - major clean-up of the Qualcomm pin control device tree bindings by
     Krzysztof

   - major header clean-up by Andy

   - some immutable irqchip clean-up for the Actions Semiconductor and
     Nuvoton drivers

   - GPIO helpers for The Cypress cy8c95x0 driver

   - bias handling in the Mediatek MT7986 driver

   - remove the unused pins-are-numbered concept that never flew"

* tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits)
  pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()
  dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
  dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered
  pinctrl: stm32: Remove check for pins-are-numbered
  pinctrl: mediatek: common: Remove check for pins-are-numbered
  pinctrl: qcom: remove duplicate included header files
  pinctrl: sunxi: d1: Add CAN bus pinmuxes
  pinctrl: loongson2: Fix some const correctness
  pinctrl: pinconf-generic: add missing of_node_put()
  pinctrl: intel: Enumerate PWM device when community has a capability
  pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
  pwm: lpss: Allow other drivers to enable PWM LPSS
  pwm: lpss: Include headers we are the direct user of
  pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
  pwm: Add a stub for devm_pwmchip_add()
  pinctrl: k210: call of_node_put()
  pinctrl: starfive: Use existing variable gpio
  dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching
  pinconf-generic: fix style issues in pin_config_param doc
  pinctrl: pinctrl-loongson2: fix Kconfig dependency
  ...
2022-12-13 13:03:06 -08:00
Linus Torvalds
01f3cbb296 SoC: DT changes for 6.2
The devicetree changes contain exactly 1000 non-merge changesets,
 including a number of new arm64 SoC variants from Qualcomm and Apple,
 as well as the Renesas r9a07g043f/u chip in both arm64 and riscv variants
 While we have occasionally merged support for non-arm SoCs in the past,
 this is now the normal path for riscv devicetree files.
 
 The most notable changes, by SoC platform, are:
 
  - The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M2 Ultra)
    chips now have initial support. This is particularly nice as I am
    typing this on a T6002 Mac Studio with only a small number of driver
    patches.
 
  - Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662), SM4250
    (Snapdragon 460), SM6375 (Snapdragon 695), SDM670 (Snapdragon 670),
    MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon 650) are all mobile
    phone chips that are closely related to others we already support.
    Adding those helps support more phones and we add several models
    from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
    3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and Google
    (Pixel 3a).  There are also new variants of the Herobrine and Trogdor
    chromebook motherboards.  SA8540P is an automotive SoC used in the
    Qdrive-3 development platform
 
  - Rockchips gains no new SoC variants, but a lot of new boards:
    three mobile gaming systems based on RK3326 Odroid-Go/rg351 family,
    two more Anbernic gaming systems based on RK3566 and a number of
    other RK356x based single-board computers.
 
  - Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
    the newly added RZ/Five is based on the same design, this now gets
    reorganized in order to share most of the dts description between
    the two and add the RZ/Five SMARC EVK board support.
 
 Aside from that, there are the usual changes all over the tree:
 
  - New boards on other platforms contain two ASpeed BMC users, two
    Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based Kobo
    Aura2 ebook reader, two i.MX8 based development boards, two Uniphier
    Pro5 development boards, the STM32MP1 testbench board from DHCOR,
    the TI K3 based BeagleBone AI-64 board, and the Mediatek Helio X10
    based Sony Xperia M5 phone.
 
  - The Starfive JH7100 source gets reorganized in order to support the
    VisionFive V1 board.
 
  - Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168,
    TI, ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
    Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
    spear, ...  The treewide cleanups now have a lot of fixes for cache
    nodes and other binding violoations.
 
  - Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm
    and Renesas platforms, adding a lot more on-chip device support
 
  - A rework of the way that DTB overlays are built.
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Merge tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "The devicetree changes contain exactly 1000 non-merge changesets,
  including a number of new arm64 SoC variants from Qualcomm and Apple,
  as well as the Renesas r9a07g043f/u chip in both arm64 and riscv
  variants.

  While we have occasionally merged support for non-arm SoCs in the
  past, this is now the normal path for riscv devicetree files.

  The most notable changes, by SoC platform, are:

   - The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M1 Ultra) chips
     now have initial support. This is particularly nice as I am typing
     this on a T6002 Mac Studio with only a small number of driver
     patches.

   - Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662),
     SM4250 (Snapdragon 460), SM6375 (Snapdragon 695), SDM670
     (Snapdragon 670), MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon
     650) are all mobile phone chips that are closely related to others
     we already support.

     Adding those helps support more phones and we add several models
     from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
     3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and
     Google (Pixel 3a).

     There are also new variants of the Herobrine and Trogdor chromebook
     motherboards. SA8540P is an automotive SoC used in the Qdrive-3
     development platform

   - Rockchips gains no new SoC variants, but a lot of new boards: three
     mobile gaming systems based on RK3326 Odroid-Go/rg351 family, two
     more Anbernic gaming systems based on RK3566 and a number of other
     RK356x based single-board computers.

   - Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
     the newly added RZ/Five is based on the same design, this now gets
     reorganized in order to share most of the dts description between
     the two and add the RZ/Five SMARC EVK board support.

  Aside from that, there are the usual changes all over the tree:

   - New boards on other platforms contain two ASpeed BMC users, two
     Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based
     Kobo Aura2 ebook reader, two i.MX8 based development boards, two
     Uniphier Pro5 development boards, the STM32MP1 testbench board from
     DHCOR, the TI K3 based BeagleBone AI-64 board, and the Mediatek
     Helio X10 based Sony Xperia M5 phone.

   - The Starfive JH7100 source gets reorganized in order to support the
     VisionFive V1 board.

   - Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168, TI,
     ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
     Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
     spear, ... The treewide cleanups now have a lot of fixes for cache
     nodes and other binding violoations.

   - Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm and
     Renesas platforms, adding a lot more on-chip device support

   - A rework of the way that DTB overlays are built"

* tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (979 commits)
  arm64: dts: apple: t6002: Fix GPU power domains
  arm64: dts: apple: t600x-pmgr: Fix search & replace typo
  arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
  arm64: dts: apple: Rename dart-sio* to sio-dart*
  arch: arm64: apple: t600x: Use standard "iommu" node name
  arch: arm64: apple: t8103: Use standard "iommu" node name
  ARM: dts: socfpga: Fix pca9548 i2c-mux node name
  dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define
  dt-bindings: iio: adc: qcom,spmi-vadc: extend example
  arm64: dts: qcom: sc8280xp: fix UFS DMA coherency
  arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie
  arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI
  arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI
  arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI
  arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI
  arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI
  arm64: dts: qcom: sm8450: align MMC node names with dtschema
  arm64: dts: qcom: sc7180-trogdor: use generic node names
  arm64: dts: qcom: sm8450-hdk: add sound support
  arm64: dts: qcom: sm8450: add Soundwire and LPASS
  ...
2022-12-12 10:21:03 -08:00
Bernhard Rosenkränzer
80b99ed74e dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
Deprecate the pins-are-numbered property

Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221129023401.278780-5-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-03 10:19:15 +01:00