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3 Commits

Author SHA1 Message Date
Geert Uytterhoeven
d9286d9743 clk: renesas: r8a774c0: Correct parent clock of DU 
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.

Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
 2019-01-24 16:01:08 +01:00
Fabrizio Castro
2a6efbc6da clk: renesas: r8a774c0: Add missing CANFD clock 
This patch adds the missing CANFD clock to the r8a774c0 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2019-01-21 13:50:40 +01:00
Fabrizio Castro
906e0a4a6d clk: renesas: cpg-mssr: Add r8a774c0 support 
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and
Software Reset support.

Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual:
Hardware (Rev. 0.61, June 12, 2018)".

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-09-19 16:42:14 +02:00