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When using clock gatings to save power, there are some known issues:
1. core clock gating (DCLCGE) must be disabled during D0 and D3 entry
and updating SRAM banks (VDRTCTL0).
2. DSP trunk clock gating (DTCGE) can cause FW crashes, disable it in D0.
To align with the new W/A flow from FW team, we must set VDRTCTL0.D3PGD
to 1 (D3 power gating disabled) at first startup and keep it all the time.
ADSP will be in D0 on first boot by BIOS part of WA. Required delays must
be preserved (waiting for HW to stabilize, after enabling CCG, changing
SRAM PG, D3PG).
D3->D0:
1. Disable core clock gating (VDRTCTL2.DCLCGE = 0)
2. Enable other CG apart from DTCG and DCLCG (VDRTCTL2. DCLCGE and DTCGE = 0)
3. Disable D3PG (VDRTCTL0.D3PGD = 1)
4. Power up necessary SRAM and wait at least for 18 clock cycles for every
bank you have powered up
5. Set D0 state(PMCS.PS = 0), wait for HW
6. Restore MCLK (clkctl.smos, disabled in D3 entry point 4)
7. Stall and reset core, set CSR
8. Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us
9. Unreset core
10.Load FW, configure PLL and other necessary things
11.Unstall core
Changing SRAM PG during D0:
1. Disable core clock gating (VDRTCTL2.DCLCGE = 0)
2. Set PG mask
3. Wait at least for 18 clock cycles for every bank you have powered up
4. Enable core clock gating, delay 50 us
D0->D3:
1. Disable core clock gating (DCLCGE = 0)
2. Stall and reset core
3. Power down entire SRAM and wait at least for 18 clock cycles for every bank
(Enable SRAM PG (ISRAMPGE = 0x3FF, DSRAMPGE = 0xFFFFF, D3SRAMPGD = 0), remember
about preserving VDRTCTL0.D3PGD = 1)
4. Shutdown PLL, disable MCLK(clkctl.smos = 0), Enable DTCG to save power
5. Set D3 state(PMCS.PS = 3), delay 50 us
6. Enable core clock gating, delay 50 us
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add PM and RTD3 support to the HSW/BDW PCM driver. The PCM driver will
now save DSP context and then power off the DSP when it's not in use.
DSP power and context is then restored when it's next used.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add generic functions to support DSP sleep, wake and stall.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Current block allocation is tied to block type and requestor type. Make the
allocation more generic by removing the struct module parameter and adding
a generic block allocator structure. Also pass in the list that the blocks
have to be added too in order to remove dependence on block requestor type.
ASoC: Intel: update scratch allocator to use generic block allocator
Update the scratch allocator to use the generic block allocator and calculate
total scratch buffer size.
ASoC: Intel: Add call to calculate offsets internally within the DSP.
A call to calculate internal DSP memory addresses used to allocate persistent
and scartch buffers.
ASoC: Intel: Add runtime module support.
Add support for runtime module objects that can be created for every FW
module that is parsed from the FW file. This gives a 1:N mapping between
the FW module from file and the runtime instantiations of that module.
We also need to make sure we remove every module and runtime module when
we unload the FW.
ASoC: Intel: Add DMA firmware loading support
Add support for DMA to load firmware modules to the DSP memory blocks.
Two DMA engines are supported, DesignWare and Intel MID.
ASoC: Intel: Add runtime module lookup API call
Add an API to allow quick lookup of runtime modules based on ID.
ASoC: Intel: Provide streams with dynamic module information
Remove the hard coded module paramaters and provide each module with
dynamically generated buffer information for scratch and persistent
buffers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add some register definitions for other shim register bits.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
HMDC is the correct naming for this register.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
the shim registers start and end can be useful while parsing the shim addresses,
so add these
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The Intel IOMMU requires that the ACPI device is used to allocate all
DMA memory buffers. This means we need to pass the DMA device pointer into child
component devices that allocate DMA memory.
We also only set the DMA mask for the ACPI device now instead of for each
component device.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
