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interrupts were improper in a previous fixes PR.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXcK4vQAKCRDj7w1vZxhR
xYicAP47+z/2soJsnUf1jahKsVFqYoxKa+Z+qYg/f/hdphEvCwD+JqY46XbjbaL7
hzHqYYQvJ1OAO/Mks3ms01/0ZnhbKww=
=9zaU
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-5.4-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
One patch to add back the PMU node that was removed because the
interrupts were improper in a previous fixes PR.
* tag 'sunxi-fixes-for-5.4-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a64: Re-add PMU node
ARM: sunxi: Fix CPU powerdown on A83T
ARM: dts: sun8i-a83t-tbs-a711: Fix WiFi resume from suspend
ARM: dts: sun7i: Drop the module clock from the device tree
dt-bindings: media: sun4i-csi: Drop the module clock
media: dt-bindings: Fix building error for dt_binding_check
arm64: dts: allwinner: a64: sopine-baseboard: Add PHY regulator delay
arm64: dts: allwinner: a64: Drop PMU node
arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay
Link: https://lore.kernel.org/r/45023fa6-b2bc-4934-b85c-3e7841dde0b1.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable L2 cache parity and ECC on a Armada XP SoC family and allow
to use in on the Armada 38x SoCs too.
- Use correct name for the rs5c372a on synology (Kirkwood based)
- Rename "sa-sram" node to "sram" on dove
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXb9ANAAKCRALBhiOFHI7
1YxGAJ42trDdNhPczQeHvNx2UcvmSKU8rQCfdNMvDGGosrbJ/aWklGPQfU4iano=
=0o2E
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt
mvebu dt for 5.5 (part 1)
- Enable L2 cache parity and ECC on a Armada XP SoC family and allow
to use in on the Armada 38x SoCs too.
- Use correct name for the rs5c372a on synology (Kirkwood based)
- Rename "sa-sram" node to "sram" on dove
* tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-xp: add label to sdram-controller node
ARM: dts: mvebu: add sdram controller node to Armada-38x
ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
ARM: dts: dove: Rename "sa-sram" node to "sram"
ARM: dts: kirkwood: synology: Fix rs5c372 RTC entry
Link: https://lore.kernel.org/r/8736f44q9l.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl29juUTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZ7rD/9XhTBgFXzd5C6yyJpjIBD/3F/4vnlK
SZ/3ZktWe9ZzwQJhMXaURxaggrTD0MXJj95/Ga03FSxtYBgb7mT6TL0m7QCnMjhR
MSekoWQaBU+MUTIUbfT/2YS1+6JTnwRxQBDD+2/qPwI6HcnJ/BIzIN7fRlAh4Xu8
TwzQdzE2pym4PPIAkiiu7iTcF468tFiRUWj01o06B/k21tHNnNqYUP/1KLY6N5pZ
oqn+FAXfgLFrmjUQi28Z+0UyAekeDl7kLmoNMUerFqI53j3+n5iosogUWznnO9NG
tN88ftULL7lA29NR7nnu++Ev5UiE/40HrpuxTcQkHLE4mNQX9eGHrhZ1/kP9ZLnN
bysYxlzr1IXZ8Mefe8Z422wQvNlQWuvNfbS0no0Xkn4H3HH0ajmYF5uv0tIna9q2
A0eWGWbhbEyuaPzSiOWMpo4Ae/bgV7PWQSdVyBluB+yX8bXoSRr8o8I3xd6uWjaY
cgF5BN32AwM44k3jgI8+HkdSxzvpdrPsxGitwpy+Yr3AW15SJ3uWA0sEemuZQ81P
+ZX+YEepCwVIgDp34oP+vWwfbGRoo3rNJrOM2CCADHQ+p1pXARKQmHRpxU2X3L35
akYNdjhvi04cIoLcP748YZYQ0Z8/Kjiofg1dMSGjmAVQZgOyF7YUrURm3x9qR6rU
yVlQPmJDj0gF5A==
=rlo7
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.5-rc1
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
* tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
ARM: tegra: trimslice: Add CPU Operating Performance Points
ARM: tegra: paz00: Add CPU Operating Performance Points
ARM: tegra: paz00: Set up voltage regulators for DVFS
ARM: tegra: Add CPU Operating Performance Points for Tegra30
ARM: tegra: Add CPU Operating Performance Points for Tegra20
ARM: tegra: Add Tegra30 CPU clock
ARM: tegra: Add Tegra20 CPU clock
ARM: tegra: Add External Memory Controller node on Tegra30
ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
ARM: tegra: Add eDP power supplies on Venice2
ARM: tegra: Add SOR0_OUT clock on Tegra124
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.
Note that this branch is based on the PRM reset driver changes branch.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl28UrgRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPQvw/+Kz/OaUWXc6NCGqbgrjvQZbJMzWykeuP3
QyIzQ/k6x9B1VqkHvnmbAUKEpROXe7/t8QaVZs2WfQLb/3QvOJtEN5KlgGOC1ofF
VLWR1aSU1bApDIbTf0tIhIEkmsm/qJvm4QlRBLahQEtP/2LRuZMybikBgbEteFMB
zgMUPjqc//gGI1Y8H90ntWlCA0runosrxJ83qJ4O74RMzBiH30h3qZFq7Xt4O/az
x0B4u+RBB3hnetq6oHBsk6TFbE0qmOBYSx81w40GM4Rn5Xgvq62PaoRHez/qLRRB
3GhtfIUb5bJX3w8wQF6wyIUQfIFjYKDut3mldx1zR01x8QwYMl5b8aD9M5MIern4
+KVT5rtjllnbMQYhOmQKky5UCKU1SOvYZDfN//4S68YF0DZ257vYFkeXIWHYA+pr
Cc8lVAgCqDV5WlBBXy2F6uZC7vQCdpPFI2ljEPryiEumJ3FlK+nY7WmpusJ6grau
BiJakyYS0dqqoJS+LH7GtB3PLChgGXIQd9SWF5NvCzbtr+4ve7dUCzTs/UitUpET
9B3kaoHE9s9UvozZkHFPxIhR7o2uAfSqUUMNCWplXy5jhPl6RFPB0myV66ai8v3U
ZVO+EAF0Bx47zz0riBlqraiMBybohohZAijZjQztHyeKE2CfBc1ErUPFAur32bF6
ML9ze/G+SkI=
=4DAS
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
PRM reset control dts changes for v5.5 merge window
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.
Note that this branch is based on the PRM reset driver changes branch.
* tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap5: Add PRM data
ARM: dts: am43xx: Add PRM data
ARM: dts: am33xx: Add PRM data
ARM: dts: omap4: add PRM nodes
ARM: dts: dra7: add PRM nodes
soc: ti: omap-prm: add omap5 PRM data
soc: ti: omap-prm: add am4 PRM data
soc: ti: omap-prm: add dra7 PRM data
soc: ti: omap-prm: add data for am33xx
soc: ti: omap-prm: add omap4 PRM data
soc: ti: omap-prm: add support for denying idle for reset clockdomain
soc: ti: omap-prm: poll for reset complete during de-assert
soc: ti: add initial PRM driver with reset control support
dt-bindings: omap: add new binding for PRM instances
Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Make sure UART3, where the console is, is called ttyS2. That is
consistent with the early console.
Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
Ponted out by DTC:
<stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges
property, but no unit name
Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
There's a typo there that rightfully upsets DTS:
<stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus
unit address format error, expected "e0000620"
Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
It should have one and DTC is indeed unhappy about its absence:
<stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or
ranges property, but no unit name
Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers
in this SoC with maximum of 32 gpios. Except GPIOC, all controllers
are capable of generating edge/level interrupts from first 8 lines.
Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is an Allwinner H3 based board, with 512MB ram, a USB OTG port,
microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI
connector.
Full details and schematic available from vendor:
http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
uart1 and uart3 had existing pin definitions for the rts/cts pairs.
Add definitions for uart2 as well.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T
This patch adds it on the Allwinner A80 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T
This patch adds it on the Allwinner A83T SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Crypto Engine is a hardware cryptographic offloader that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on
Cardhu A04.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Set minimum and maximum voltages, and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available
now on TrimSlice.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on
AC100.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary for them.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary, like for example
in a case of tegra20-trimslice which is outlet-powered device.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1,
which was missed due to the clock driver bug that is fixed now in all of
stable kernels.
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The power supplies needed to drive eDP on Venice2 were never hooked up,
so things only worked because those regulators are already enabled by
other devices.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the stmpe-adc DT node as found on Toradex T30 modules
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Without enabling keep-power-in-suspend, we can't wake the device
up using WOL packet, and the log is flooded with these messages
on resume:
sunxi-mmc 1c10000.mmc: send stop command failed
sunxi-mmc 1c10000.mmc: data error, sending stop command
sunxi-mmc 1c10000.mmc: send stop command failed
sunxi-mmc 1c10000.mmc: data error, sending stop command
So to make the WiFi really a wakeup-source, we need to keep it powered
during suspend.
Fixes: 0e23372080def7 ("arm: dts: sun8i: Add the TBS A711 tablet devicetree")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Highlights:
----------
MPU part:
-Add and enable ADC support on stm32mp157a-dk1
-Add DAC support on stm32mp157c-ed1
-Add and enable VREFBUF support on stm32mp157a-dk1
-Add focaltech touchscreen on stm32mp157c-dk2
-Add hdmi support on stm32mp157a-dk1
-Fix issues seen during YAML DT validation
-Fix regulators issues for all MPU boards
MCU part:
-Fix issues seen during YAML DT validation
-----BEGIN PGP SIGNATURE-----
iQJMBAABCgA2FiEEctl9+nxzUSUqdELdf5rJavIecIUFAl2y7XIYHGFsZXhhbmRy
ZS50b3JndWVAc3QuY29tAAoJEH+ayWryHnCFy20P/jsx+9tDLGZAHCiPlnIu80gd
XKjecdpVPTYYCef4cUxF6rkkJWbtdauvmys9xJH9EZetd0kwPF6otfo6hiQGsIB1
+3ChAEzI6qHV5iEWl91AWCIyTuVo6dimJqXJCNLuldDMQbOlEbP4jHjD00ggn0r3
tFhvhp/gXT21xt+t0kgHf3GJV8nQwwQw3NHCoqagnzHRZrURgwZM/ecYJs7uv3eu
TGMmuNytxFl46JugVnWFYj2NgMrg/G0oqDR7SwieoEBqADEmkPDS2UkKPmuAe9BO
3sknTu1Mf1yXlbWLeFOa9MLgiNRH7c5oLSWPkRnFe/GMlco0iJ+63r1ff4N5i5u0
M5l0dJ0mL81RK6n1rubyaOdMBV25UIZ2QlL13tTPmVFbUj95pR9d4B6sxaqdJh3a
8s6WYLnlyJZ8+WldcPURYCot4ezRy9o0vE5YN/FCW3NDdY0fEYXQVCbs/ufgmKNk
K7jRleAr0SXk5IFRYgVxvkhbYWB80jKVPEGEhpBPAzrhvSmJqgHN2RdUXB+IRGyP
IIFZT8UgodMxzrxA9bJStphet4nvItGW68G76FDXt2zS1rw4mLum6rKq+s3x3Fyp
DiUP7ZfaaKLQbo/nG+AAIK4I3lWgI+lxG7uF5tG/6qFOyTqKmMiMXUFK7jisMZeQ
yyyhkjAZXjBtmcKpXbgV
=X4PA
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.5, round 1
Highlights:
----------
MPU part:
-Add and enable ADC support on stm32mp157a-dk1
-Add DAC support on stm32mp157c-ed1
-Add and enable VREFBUF support on stm32mp157a-dk1
-Add focaltech touchscreen on stm32mp157c-dk2
-Add hdmi support on stm32mp157a-dk1
-Fix issues seen during YAML DT validation
-Fix regulators issues for all MPU boards
MCU part:
-Fix issues seen during YAML DT validation
* tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: remove useless dma-ranges property for stm32f469
ARM: dts: stm32: remove useless dma-ranges property for stm32f429
ARM: dts: stm32: disable active-discharge for vbus_otg on stm32mp157a-avenger96
ARM: dts: stm32: Fix active discharge usage on stm32mp157
ARM: dts: stm32: change default minimal buck1 value on stm32mp157
ARM: dts: stm32: add PWR regulators support on stm32mp157
ARM: dts: stm32: remove useless interrupt from dsi node for stm32f469
ARM: dts: stm32: add hdmi audio support to stm32mp157a-dk1 board
ARM: dts: stm32: Add DAC support to stm32mp157c-ed1
ARM: dts: stm32: Add DAC pins used on stm32mp157c-ed1
ARM: dts: stm32: fix regulator-sd_switch node on stm32mp157c-ed1 board
ARM: dts: stm32: remove usb phy-names entries on stm32mp157c-ev1
ARM: dts: stm32: fix joystick node on stm32f746 and stm32mp157c eval boards
ARM: dts: stm32: fix memory nodes to match with DT validation tool
ARM: dts: stm32: add focaltech touchscreen on stm32mp157c-dk2 board
ARM: dts: stm32: enable ADC support on stm32mp157a-dk1
ARM: dts: stm32: add ADC pins used on stm32mp157a-dk1
ARM: dts: stm32: Enable VREFBUF on stm32mp157a-dk1
ARM: dts: stm32: move ltdc pinctrl on stm32mp157a dk1 board
Link: https://lore.kernel.org/r/02c39510-f36d-abbb-c76f-49aff07c0a08@st.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Remove dma-ranges from ltdc node since it is already set
on bus node.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Remove dma-ranges from ltdc node since it is already set
on bus node.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Active discharge is not needed on vbus_otg and generate unneeded current
consumption.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Minimal value is the value set during boot or before suspend.
We must ensure that the value is a functional value to boot.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This patch adds support of STM32 PWR regulators on
stm32mp157c. This replace dummy fixed regulators on
stm32mp157c-ed1 and stm32mp157c-dk2.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
DSI driver doesn't use interrupt, remove it from the node since it
breaks yaml check.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
stm32mp157c-ed1 board has digital-to-analog converter signals routed
to JP11 and JP10 jumpers (e.g. PA4/PA5).
It's easier then to configure them both. But keep them disabled by default,
so the pins are kept in their initial state to lower power consumption.
This way they can also be used as GPIO.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Define pins that can be used by digital-to-analog converter on
stm32mp157c eval daughter board:
- PA4 and PA5 pins are available respectively on JP11 and JP10
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
"phy-names" entries are not used. To be compliant with DT validation
tool, those entries have to be remove.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
"#size-cells" entry is not needed for "gpio-keys" driver. Indeed "reg"
entry is not used. This commit will fix a warnings seen by DT validation
tool.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
