5384 Commits

Author SHA1 Message Date
Linus Walleij
fbfc5fc351 Samsung pinctrl drivers changes for v5.18
1. Fix OF reference leak in pinctrl driver probe error path.
 2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks.
 3. Accept devicetrees with GPIO pin bank definitions named with a
    "-gpio-bank" suffix.  This is necessary for later Samsung pinctrl
    bindings dtschema.
 4. Convert Samsung pinctrl bindings to dtschema.
 5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts.
 6. Add support for Tesla FSD SoC.
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Merge tag 'samsung-pinctrl-5.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v5.18

1. Fix OF reference leak in pinctrl driver probe error path.
2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks.
3. Accept devicetrees with GPIO pin bank definitions named with a
   "-gpio-bank" suffix.  This is necessary for later Samsung pinctrl
   bindings dtschema.
4. Convert Samsung pinctrl bindings to dtschema.
5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts.
6. Add support for Tesla FSD SoC.
2022-02-19 02:05:02 +01:00
Shawn Guo
c981a78944 pinctrl: qcom: qcm2290: Add GPIO wakeirq map
It adds the map of wakeup capable GPIOs and the pins at MPM wake
controller on QCM2290, so that these GPIOs can wake up the SoC from
vlow/vmin low power mode.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20211122080938.20623-1-shawn.guo@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-19 01:59:19 +01:00
Jonathan Marek
06e12b7928 pinctrl: qcom: print egpio mode in debugfs
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and
the APSS TLMM settings are ignored. Reflect that in the debugfs dump.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-19 01:53:55 +01:00
Jonathan Marek
c74803ee45 pinctrl: qcom: sm8450: Add egpio support
This mirrors egpio support added for sc7280. This change is necessary for
gpios 165 to 209 to be driven by APSS.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-1-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-19 01:53:55 +01:00
Linus Walleij
8d4c0d185a pinctrl: renesas: Updates for v5.18
- Add MOST (MediaLB I/F) pins on R-Car E3 and D3,
   - Add support for the new RZ/V2L SoC,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.18

  - Add MOST (MediaLB I/F) pins on R-Car E3 and D3,
  - Add support for the new RZ/V2L SoC,
  - Miscellaneous fixes and improvements.
2022-02-19 01:49:03 +01:00
Jonathan Neuschäfer
603501c164 pinctrl: nuvoton: npcm7xx: Rename DS() macro to DSTR()
The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h,
which results in a compiler warning when build-testing on ARCH=um.
Rename this driver's "DS" macro to DSTR so avoid this collision.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 02:03:53 +01:00
Jonathan Neuschäfer
9d0f18bca3 pinctrl: nuvoton: npcm7xx: Use %zu printk format for ARRAY_SIZE()
When compile-testing on 64-bit architectures, GCC complains about the
mismatch of types between the %d format specifier and value returned by
ARRAY_LENGTH(). Use %zu, which is correct everywhere.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-2-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 02:03:53 +01:00
kernel test robot
9c03e49e0c pinctrl: starfive: fix semicolon.cocci warnings
drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Reported-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 01:47:54 +01:00
Kunihiko Hayashi
923fe8abb0 pinctrl: uniphier: Add USB device pinmux settings
Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for
ports 0 and 1 support USB device mode.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 01:37:21 +01:00
Kunihiko Hayashi
dfc04955c8 pinctrl: uniphier: Divide pinmux group to support 1ch and 2ch I2S
Current pinmux group for audio in/out assumes 4ch I2S case but the
UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current
ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other
ain and aout in the same way.

Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-3-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 01:37:21 +01:00
Kunihiko Hayashi
8e703784ed pinctrl: uniphier: Add missing audio pinmux settings for PXs2 SoC
Add missing audio I/O pinmux settings for PXs2 SoC.
This adds ain1 4ch pins, ain3 and aout1.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 01:37:21 +01:00
Rayyan Ansari
d8420f5a25 pinctrl: qcom: spmi-mpp: Add PM8226 compatible
The PM8226 provides 8 MPPs.
Add a compatible to support them.

Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220124171538.18088-2-rayyan@ansari.sh
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11 01:08:06 +01:00
Biju Das
2e08ab0427 pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()
Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with different port pin definitions(eg:- RZ/G2UL SoC has
fewer ports compared to RZ/G2L and port pin definitions are
different).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
5a2a1c7139 pinctrl: renesas: r8a77995: Restore pin group sort order
Move the msiof* pin groups where they belong.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/da1018c56134b910121b085b736fe7f664b96df1.1643199959.git.geert+renesas@glider.be
2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
8313b5e71e pinctrl: renesas: r8a7790: Restore pin function sort order
Move the du* pin function where it belongs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f4eb545cedcd1a72f0f80ef85daf03e2e423e90f.1643199959.git.geert+renesas@glider.be
2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
4af28d905f pinctrl: renesas: r8a7779: Restore pin function sort order
Move the sdhi* pin functions where they belong.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f69d05a760445c8d67bedcb39cf5959333c71a1f.1643199959.git.geert+renesas@glider.be
2022-02-08 09:54:44 +01:00
Geert Uytterhoeven
652ef476d1 pinctrl: renesas: r8a779a0: Rename MOD_SEL2_* definitions
Rename the MOD_SEL2_* definitions, to match the bitfield order in
IPxSRy_* definitions and in MOD_SEL* definitions in other drivers.

No changes in generated code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
2022-02-08 09:54:44 +01:00
Biju Das
0c8fce49f2 pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin control support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-08 09:54:04 +01:00
Horatiu Vultur
8fc0bfcd57 pinctrl: ocelot: Add support for ServalT SoC
This patch adds support for ServalT pinctrl, using the ocelot driver as
basis.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220125131858.309237-3-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-03 00:38:28 +01:00
Martin Jücker
3652dc070b pinctrl: samsung: improve wake irq info on console
Improve the wake irq message by also printing the bank name and hwirq
number that matches this irq number.

Signed-off-by: Martin Jücker <martin.juecker@gmail.com>
Link: https://lore.kernel.org/r/20220130232122.GA119248@adroid
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-02-01 09:13:30 +01:00
Wells Lu
aa74c44be1 pinctrl: Add driver for Sunplus SP7021
Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu <wellslutw@gmail.com>
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-30 02:55:41 +01:00
Qianggui Song
775214d389 pinctrl: meson: add pinctrl driver support for Meson-S4 Soc
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-30 02:52:45 +01:00
Alim Akhtar
0d1b662c37 pinctrl: samsung: add FSD SoC specific data
Adds Tesla FSD SoC specific data to enable pinctrl.
FSD SoC has similar pinctrl controller as found in the most
Samsung/Exynos SoCs.

Cc: linux-fsd@tesla.com
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-13-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-25 18:08:57 +01:00
Rafał Miłecki
f7e322d99f pinctrl: bcm: add driver for BCM4908 pinmux
BCM4908 has its own pins layout so it needs a custom binding and a Linux
driver.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-25 01:42:13 +01:00
Nikita Yushchenko
96310a120c pinctrl: renesas: r8a7799[05]: Add MediaLB pins
This adds pins, groups, and functions for MediaLB devices on Renesas
R-Car E3 and D3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225191713.2187975-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24 09:59:43 +01:00
Geert Uytterhoeven
30d369991b pinctrl: renesas: r8a7791: Remove INTC_IRQx_N
The INTC_IRQx_N pin functions were only documented in preliminary
versions of the R-Car M2 Hardware User's Manual, and were never used.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/932834b388887e1ae267e5a852c688c79091a5f9.1640269369.git.geert+renesas@glider.be
2022-01-24 09:59:43 +01:00
Geert Uytterhoeven
c038a988a8 pinctrl: renesas: r8a7790: Remove INTC_IRQx_N
The INTC_IRQx_N pin functions were only documented in preliminary
versions of the R-Car H2 Hardware User's Manual, and were never used.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5b3fb0c025eaca037a53120fee811cf13e08b55f.1640269218.git.geert+renesas@glider.be
2022-01-24 09:59:43 +01:00
Wolfram Sang
9ca70f4202 pinctrl: renesas: rcar: Do not enforce GPIO if already muxed
For Renesas PFCs not setting .strict, we can snoop GPIOs which are
already muxed to some other function.  To actually make use of that, we
shouldn't mux them back to GPIO if they have been already muxed to
something.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211210113226.40111-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24 09:59:42 +01:00
Lad Prabhakar
c00cdc32e7 pinctrl: at91-pio4: Use platform_get_irq() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.

In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().

While at it, replace the dev_err() with dev_dbg() as platform_get_irq()
prints an error message upon error.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220104140913.29699-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24 01:12:54 +01:00
Manivannan Sadhasivam
b9dc88de4d pinctrl: qcom: Return -EINVAL for setting affinity if no IRQ parent
The MSM GPIO IRQ controller relies on the parent IRQ controller to set the
CPU affinity for the IRQ. And this is only valid if there is any wakeup
parent available and defined in DT.

For the case of no parent IRQ controller defined in DT,
msm_gpio_irq_set_affinity() and msm_gpio_irq_set_vcpu_affinity() should
return -EINVAL instead of 0 as the affinity can't be set.

Otherwise, below warning will be printed by genirq:

genirq: irq_chip msmgpio did not update eff. affinity mask of irq 70

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220113162617.131697-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24 01:12:54 +01:00
Gary Bisson
46f3418926 pinctrl: meson-g12a: add more pwm_f options
Add missing PWM_F pin muxing for GPIOA_11 and GPIOZ_12.

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220112211642.2248901-2-gary.bisson@boundarydevices.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24 01:12:54 +01:00
Minghao Chi
02f23aa47a drivers/pinctrl: remove redundant ret variable
Return value from pxa2xx_pinctrl_init() directly instead
of taking this in another redundant variable.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Signed-off-by: CGEL ZTE <cgel.zte@gmail.com>
Link: https://lore.kernel.org/r/20220110012730.643927-1-chi.minghao@zte.com.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24 01:12:54 +01:00
Krzysztof Kozlowski
832ae134cc pinctrl: samsung: add support for Exynos850 and ExynosAutov9 wake-ups
It seems that newer ARMv8 Exynos SoC like Exynos850 and
ExynosAutov9 have differences of their pin controller node capable of
external wake-up interrupts:
1. No multiplexed external wake-up interrupt, only direct,
2. More than one pin controller capable of external wake-up interrupts.

Add support for dedicated Exynos850 and ExynosAutov9 compatibles.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20220111201722.327219-20-krzysztof.kozlowski@canonical.com
2022-01-23 12:21:56 +01:00
Krzysztof Kozlowski
a29681b0cc pinctrl: samsung: accept GPIO bank nodes with a suffix
Existing dt-bindings expected that each GPIO/pin bank within pin
controller has its own node with name matching the bank (e.g. gpa0,
gpx2) and "gpio-controller" property.  The node name is then used for
matching between driver data and DTS.

Newly introduced dtschema expects to have nodes ending with "-gpio-bank"
suffix, so rewrite bank-devicetree matching to look for old and new
style of naming.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20220111201426.326777-3-krzysztof.kozlowski@canonical.com
2022-01-23 12:21:56 +01:00
Sam Protsenko
96f7993501 pinctrl: samsung: Remove EINT handler for Exynos850 ALIVE and CMGP gpios
GPIO_ALIVE and GPIO_CMGP blocks in Exynos850 SoC don't have EINT
capabilities (like EINT_SVC register), and there are no corresponding
interrupts wired to GIC. Instead those blocks have wake-up interrupts
for each pin. The ".eint_gpio_init" callbacks were specified by mistake
for these blocks, when porting pinctrl code from downstream kernel. That
leads to error messages like this:

    samsung-pinctrl 11850000.pinctrl: irq number not available

Remove ".eint_gpio_init" for pinctrl_alive and pinctrl_gpmc to fix this
error. This change doesn't affect proper interrupt handling for related
pins, as all those pins are handled in ".eint_wkup_init".

Fixes: cdd3d945dcec ("pinctrl: samsung: Add Exynos850 SoC specific data")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20220114203757.4860-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-23 12:21:56 +01:00
Krzysztof Kozlowski
50ebd19e35 pinctrl: samsung: drop pin banks references on error paths
The driver iterates over its devicetree children with
for_each_child_of_node() and stores for later found node pointer.  This
has to be put in error paths to avoid leak during re-probing.

Fixes: ab663789d697 ("pinctrl: samsung: Match pin banks with their device nodes")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20220111201426.326777-2-krzysztof.kozlowski@canonical.com
2022-01-23 12:21:56 +01:00
Linus Torvalds
e3084ed48f Pin control bulk changes for the v5.17 kernel cycle
Core changes:
 
 - New standard enumerator and corresponding device tree bindings
   for output impedance pin configuration. (Implemented and used
   in the Renesas rzg2l driver.)
 
 - Cleanup of Kconfig and Makefile to be somewhat orderly and
   alphabetic.
 
 New drivers:
 
 - Samsung Exynos 7885 pin controller.
 
 - Ocelot LAN966x pin controller.
 
 - Qualcomm SDX65 pin controller.
 
 - Qualcomm SM8450 pin controller.
 
 - Qualcomm PM8019, PM8226 and PM2250 pin controllers.
 
 - NXP/Freescale i.MXRT1050 pin controller.
 
 - Intel Thunder Bay pin controller.
 
 Enhancements:
 
 - Introduction of the string library helper function
   "kasprintf_strarray()" and subsequent use in Rockchip, ST and
   Armada pin control drivers, as well as the GPIO mockup driver.
 
 - The Ocelot pin controller has been extensively rewritten to
   use regmap and other modern kernel infrastructure.
 
 - The Microchip SGPIO driver has been converted to use regmap.
 
 - The SPEAr driver had been converted to use regmap.
 
 - Substantial cleanups and janitorial on the Apple pin control
   driver that was merged for v5.16.
 
 - Janitorial to remove of_node assignments in the GPIO portions
   that anyway get this handled in the GPIO core.
 
 - Minor cleanups and improvements in several pin controllers.
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Merge tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control bulk updates from Linus Walleij:
 "Core changes:

   - New standard enumerator and corresponding device tree bindings for
     output impedance pin configuration. (Implemented and used in the
     Renesas rzg2l driver.)

   - Cleanup of Kconfig and Makefile to be somewhat orderly and
     alphabetic.

  New drivers:

   - Samsung Exynos 7885 pin controller.

   - Ocelot LAN966x pin controller.

   - Qualcomm SDX65 pin controller.

   - Qualcomm SM8450 pin controller.

   - Qualcomm PM8019, PM8226 and PM2250 pin controllers.

   - NXP/Freescale i.MXRT1050 pin controller.

   - Intel Thunder Bay pin controller.

  Enhancements:

   - Introduction of the string library helper function
     "kasprintf_strarray()" and subsequent use in Rockchip, ST and
     Armada pin control drivers, as well as the GPIO mockup driver.

   - The Ocelot pin controller has been extensively rewritten to use
     regmap and other modern kernel infrastructure.

   - The Microchip SGPIO driver has been converted to use regmap.

   - The SPEAr driver had been converted to use regmap.

   - Substantial cleanups and janitorial on the Apple pin control driver
     that was merged for v5.16.

   - Janitorial to remove of_node assignments in the GPIO portions that
     anyway get this handled in the GPIO core.

   - Minor cleanups and improvements in several pin controllers"

* tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits)
  pinctrl: imx: fix assigning groups names
  dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations
  pinctrl: bcm: ns: use generic groups & functions helpers
  pinctrl: imx: fix allocation result check
  pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
  pinctrl: Propagate firmware node from a parent device
  dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
  pinctrl: add one more "const" for generic function groups
  pinctrl: keembay: rework loops looking for groups names
  pinctrl: keembay: comment process of building functions a bit
  pinctrl: imx: prepare for making "group_names" in "function_desc" const
  ARM: dts: gpio-ranges property is now required
  pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED
  pinctrl: Get rid of duplicate of_node assignment in the drivers
  pinctrl-sunxi: don't call pinctrl_gpio_direction()
  pinctrl-bcm2835: don't call pinctrl_gpio_direction()
  pinctrl: bcm2835: Silence uninit warning
  pinctrl: Sort Kconfig and Makefile entries alphabetically
  pinctrl: Add Intel Thunder Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver
  ...
2022-01-12 10:56:08 -08:00
Linus Torvalds
bb4ed26e7e SoC: Add support for StarFive JH7100 RISC-V SoC
This adds support for the StarFive JH7100, including the necessary
 device drivers and DT files for the BeagleV Starlight prototype
 board, with additional boards to be added later. This SoC promises
 to be the first usable low-cost platform for RISC-V.
 
 I've taken this through the SoC tree in the anticipation of adding
 a few other Arm based SoCs as well, but those did not pass the
 review in time, so it's only this one.
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Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull RISC-V SoC updates from Arnd Bergmann:
 "Add support for StarFive JH7100 RISC-V SoC

  This adds support for the StarFive JH7100, including the necessary
  device drivers and DT files for the BeagleV Starlight prototype board,
  with additional boards to be added later. This SoC promises to be the
  first usable low-cost platform for RISC-V.

  I've taken this through the SoC tree in the anticipation of adding a
  few other Arm based SoCs as well, but those did not pass the review in
  time, so it's only this one"

* tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  reset: starfive-jh7100: Fix 32bit compilation
  RISC-V: Add BeagleV Starlight Beta device tree
  RISC-V: Add initial StarFive JH7100 device tree
  serial: 8250_dw: Add StarFive JH7100 quirk
  dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
  pinctrl: starfive: Add pinctrl driver for StarFive SoCs
  dt-bindings: pinctrl: Add StarFive JH7100 bindings
  dt-bindings: pinctrl: Add StarFive pinctrl definitions
  reset: starfive-jh7100: Add StarFive JH7100 reset driver
  dt-bindings: reset: Add Starfive JH7100 reset bindings
  dt-bindings: reset: Add StarFive JH7100 reset definitions
  clk: starfive: Add JH7100 clock generator driver
  dt-bindings: clock: starfive: Add JH7100 bindings
  dt-bindings: clock: starfive: Add JH7100 clock definitions
  dt-bindings: interrupt-controller: Add StarFive JH7100 plic
  dt-bindings: timer: Add StarFive JH7100 clint
  RISC-V: Add StarFive SoC Kconfig option
2022-01-10 08:32:37 -08:00
Rafał Miłecki
7442936633 pinctrl: imx: fix assigning groups names
This fixes regression caused by incorrect array indexing.

Reported-by: Fabio Estevam <festevam@gmail.com>
Fixes: 02f117134952 ("pinctrl: imx: prepare for making "group_names" in "function_desc" const")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Tested-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20211227122237.6363-1-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-02 07:33:51 +01:00
Linus Walleij
c8eefdbfa1 Samsung pinctrl drivers changes for v5.17
1. Add support for Exynos7885.
 2. Drop usage of platform_get_resource().
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Merge tag 'samsung-pinctrl-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v5.17

1. Add support for Exynos7885.
2. Drop usage of platform_get_resource().
2021-12-26 04:34:01 +01:00
Rafał Miłecki
4b1643cb57 pinctrl: bcm: ns: use generic groups & functions helpers
This simplifies ns driver and gets rid of ~70 lines of code.

"const" had to be dropped from "struct ns_pinctrl_group" @pins to match
"struct group_desc" @pins and pinctrl_generic_add_group(). Otherwise it
would cause:

drivers/pinctrl/bcm/pinctrl-ns.c: In function 'ns_pinctrl_probe':
drivers/pinctrl/bcm/pinctrl-ns.c:277:13: warning: passing argument 3 of 'pinctrl_generic_add_group' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
  277 |        group->pins, group->num_pins, NULL);
      |        ~~~~~^~~~~~

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20211222064344.14624-1-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-26 04:22:11 +01:00
Rafał Miłecki
aa63e6562a pinctrl: imx: fix allocation result check
Fix code to check correct variable value.

Reported-by: Abel Vesa <abel.vesa@nxp.com>
Fixes: 02f117134952 ("pinctrl: imx: prepare for making "group_names" in "function_desc" const")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20211222212807.27122-1-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-26 04:19:23 +01:00
Lad Prabhakar
a382d568f1 pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.

In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_optional().

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211224145748.18754-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-25 11:18:06 +01:00
Andy Shevchenko
ce85283733 pinctrl: Propagate firmware node from a parent device
When creating MFD platform devices the firmware node is left unset.
This, in particular, prevents GPIO library to use it for different
purposes. Propagate firmware node from the parent device and let
GPIO library do the right thing.

While at it, slightly modify the headers to reflect the usage of APIs.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Link: https://lore.kernel.org/r/20211216151227.58687-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-22 03:09:56 +01:00
Rafał Miłecki
bd0aae66c4 pinctrl: add one more "const" for generic function groups
Generic code doesn't modify those strings and .get_function_groups
callback has that extra "const" as well. This allows more flexibility in
GENERIC_PINMUX_FUNCTIONS users.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20211216162206.8027-4-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-22 02:57:27 +01:00
Rafał Miłecki
c26c4bfc10 pinctrl: keembay: rework loops looking for groups names
Make the outer loop iterate over functions as that's the real subject.
This simplifies code (and reduces amount of lines of code) as allocating
memory for names doesn't require extra checks anymore.

While at it use local "group_names" variable. The plan for
"struct function_desc" is to make its "group_names" /double/ const. That
will allow drivers to use it with static const data.

This keembay "group_names" change is required to avoid:
drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_add_functions':
drivers/pinctrl/pinctrl-keembay.c:1594:8: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
 1594 |    grp = func->group_names;
      |        ^

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20211216162206.8027-3-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-22 02:57:27 +01:00
Rafał Miłecki
5d0674999c pinctrl: keembay: comment process of building functions a bit
This should make code a bit easier to follow. While at it use some "for"
loops to simplify array iteration loops.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20211216162206.8027-2-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-22 02:57:27 +01:00
Rafał Miłecki
02f1171349 pinctrl: imx: prepare for making "group_names" in "function_desc" const
The plan for "struct function_desc" is to make its "group_names"
/double/ const. That will allow drivers to use it with static const
data.

This imx change is required to avoid:
drivers/pinctrl/freescale/pinctrl-imx.c: In function 'imx_pinctrl_parse_functions':
drivers/pinctrl/freescale/pinctrl-imx.c:672:24: error: assignment of read-only location '*(func->group_names + (sizetype)(i * 4))'
  672 |   func->group_names[i] = child->name;
      |                        ^

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20211216162206.8027-1-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-22 02:57:27 +01:00
Linus Walleij
facb4e40e4 pinctrl: renesas: Updates for v5.17 (take two)
- Align comments in the R-Car V3U pin control driver.
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Merge tag 'renesas-pinctrl-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.17 (take two)

  - Align comments in the R-Car V3U pin control driver.
2021-12-20 03:14:33 +01:00
Arnd Bergmann
4c07777123 Basic StarFive JH7100 RISC-V SoC support
This adds support for the StarFive JH7100 RISC-V SoC. The SoC has many
 devices that need non-coherent DMA operations to work which isn't
 upstream yet[1], so this just adds basic support to boot up, get a
 serial console, blink an LED and reboot itself. Unlike the Allwinner D1
 this chip doesn't use any extra pagetable bits, but instead the DDR RAM
 appears twice in the memory map, with and without the cache.
 
 The JH7100 is a test chip for the upcoming JH7110 and about 300 BeagleV
 Starlight Beta boards were sent out with them as part of a now cancelled
 BeagleBoard.org project. However StarFive has produced more of the
 JH7100s and will be selling VisionFive boards with them soon[2].
 
 [1]: https://lore.kernel.org/linux-riscv/20210723214031.3251801-2-atish.patra@wdc.com/
 [2]: https://www.cnx-software.com/2021/12/09/starfive-visionfive-single-board-computer-for-sale-accelerating-risc-v-ecosystem-development/
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Merge tag 'jh7100-for-5.17' of https://github.com/esmil/linux into arm/newsoc

Basic StarFive JH7100 RISC-V SoC support

This adds support for the StarFive JH7100 RISC-V SoC. The SoC has many
devices that need non-coherent DMA operations to work which isn't
upstream yet[1], so this just adds basic support to boot up, get a
serial console, blink an LED and reboot itself. Unlike the Allwinner D1
this chip doesn't use any extra pagetable bits, but instead the DDR RAM
appears twice in the memory map, with and without the cache.

The JH7100 is a test chip for the upcoming JH7110 and about 300 BeagleV
Starlight Beta boards were sent out with them as part of a now cancelled
BeagleBoard.org project. However StarFive has produced more of the
JH7100s and will be selling VisionFive boards with them soon[2].

[1]: https://lore.kernel.org/linux-riscv/20210723214031.3251801-2-atish.patra@wdc.com/
[2]: https://www.cnx-software.com/2021/12/09/starfive-visionfive-single-board-computer-for-sale-accelerating-risc-v-ecosystem-development/

* tag 'jh7100-for-5.17' of https://github.com/esmil/linux:
  RISC-V: Add BeagleV Starlight Beta device tree
  RISC-V: Add initial StarFive JH7100 device tree
  serial: 8250_dw: Add StarFive JH7100 quirk
  dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
  pinctrl: starfive: Add pinctrl driver for StarFive SoCs
  dt-bindings: pinctrl: Add StarFive JH7100 bindings
  dt-bindings: pinctrl: Add StarFive pinctrl definitions
  reset: starfive-jh7100: Add StarFive JH7100 reset driver
  dt-bindings: reset: Add Starfive JH7100 reset bindings
  dt-bindings: reset: Add StarFive JH7100 reset definitions
  clk: starfive: Add JH7100 clock generator driver
  dt-bindings: clock: starfive: Add JH7100 bindings
  dt-bindings: clock: starfive: Add JH7100 clock definitions
  dt-bindings: interrupt-controller: Add StarFive JH7100 plic
  dt-bindings: timer: Add StarFive JH7100 clint
  RISC-V: Add StarFive SoC Kconfig option

Link: https://lore.kernel.org/r/20211216164205.286138-1-kernel@esmil.dk
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16 17:51:38 +01:00