61355 Commits

Author SHA1 Message Date
Linus Walleij
1b56b17f99 ARM: 7084/1: mach-integrator: retire some timer macros
These macros are not used by anything since the switch to
generic time in commit b9cedda230793cbf58eb012ddadedd490cc8e129
so let's retire them.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:42 +01:00
Peter Hüwe
a7b0ab5bd0 ARM: 7078/1: Footbridge: Sort KConfig Options alphabetically
As per request of rmk, the options should be sorted alphabetically.

Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:42 +01:00
Jochen Friedrich
d056f5a8fe ARM: 7026/1: simpad: replace ARM specific LED code
Remove the legacy ARM LED code for simpad devices and
register a stadard LED platform device using GPIO line
instead.

Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:42 +01:00
Jochen Friedrich
dbd406f9d0 ARM: 7025/1: simpad: add GPIO based device definitions.
Register keyboard, polled keyboard and I2C platform
devices based on GPIOs.

Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:42 +01:00
Jochen Friedrich
de0bc0d1b0 ARM: 7024/1: simpad: Cleanup CS3 accessors.
- prepend CS3 accessors by simpad_ to indicate they
  are specific to simpad devices.
- use spinlock to protect shadow register.
- implement 8 read-only pins.
- use readl/writel macros so barriers are used where
  necessary.
- register CS3 as GPIO controller with 24 pins
  (16 output only and 8 input only).
- fix PCMCIA driver to access the read-only pins
  rather than the shadow register for status bits.

Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:42 +01:00
Jochen Friedrich
f24dec9fda ARM: 7027/1: simpad: Add ucb1x00 GPIO definitions and register GPIO
Add ucb1x00 GPIO definitions to simpad.h and add gpio_base
to ucb1x00 platform device so the pins are available using
the GPIO API.

Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:41 +01:00
Laura Abbott
b380ab4f85 ARM: 7068/1: process: change from __backtrace to dump_stack in show_regs
Currently, show_regs calls __backtrace which does
nothing if CONFIG_FRAME_POINTER is not set. Switch to
dump_stack which handles both CONFIG_FRAME_POINTER and
CONFIG_ARM_UNWIND correctly.

__backtrace is now superseded by dump_stack in general
and show_regs was the last caller so remove __backtrace
as well.

Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:41 +01:00
Nick Bowler
b3377d1865 ARM: 7064/1: vexpress: Use wfi macro in platform_do_lowpower.
Current Versatile Express CPU hotplug code includes a hardcoded WFI
instruction, in ARM encoding.  When the kernel is compiled in Thumb-2
mode, this is invalid and causes the machine to hang hard when a CPU
is offlined.

Using the wfi macro (which uses the appropriate assembler mnemonic)
causes the correct instruction to be emitted in either case.  As a
consequence of this change, an apparently vestigial "cc" clobber is
dropped from the asm (the macro uses "memory" only).

Signed-off-by: Nick Bowler <nbowler@elliptictech.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:41 +01:00
Dave Martin
ef4c53687e ARM: 7031/1: entry: Fix Thumb-2 undef handling for multi-CPU kernels
When v6 and >=v7 boards are supported in the same kernel, the
__und_usr code currently makes a build-time assumption that Thumb-2
instructions occurring in userspace don't need to be supported.
Strictly speaking this is incorrect.

This patch fixes the above case by doing a run-time check on the
CPU architecture in these cases.  This only affects kernels which
support v6 and >=v7 CPUs together: plain v6 and plain v7 kernels
are unaffected.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Jon Medhurst <tixy@yxit.co.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:41 +01:00
Dave Martin
85519189df ARM: 7030/1: entry: Remove unnecessary masking when decoding Thumb-2 instructions
When testing whether a Thumb-2 instruction is 32 bits long or not,
the masking done in order to test bits 11-15 of the first
instruction halfword won't affect the result of the comparison, so
remove it.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Dave Martin
2ecccf90f2 ARM: 7029/1: Make cpu_architecture into a global variable
The CPU architecture really should not be changing at runtime, so
make it a global variable instead of a function.

The cpu_architecture() function declared in <asm/system.h> remains
the correct way to read this variable from C code.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Jon Medhurst <tixy@yxit.co.uk>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Sascha Hauer
40c6d8aee4 ARM: 7022/1: allow to detect conflicting zreladdrs
Boards used to specify zreladdr in their Makefile.boot with
zreladdr-y := x, so conflicting zreladdrs were silently overwritten.
This patch changes this to zreladdr-y += x, so that we end
up with multiple words in zreladdr in such a case. We can
detect this later and complain if necessary.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Sascha Hauer
cd227fbffa ARM: 7021/1: Check for multiple load addresses before building a uImage
uImages need a load address specified. This makes them
incompatible with multiple zreladdrs. Catch this error
before building an uImage so that we do not end up with
broken uImages. The load address can still be specified
with LOADADDR= on the command line.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Sascha Hauer
60aac93283 ARM: 7020/1: Check for multiple zreladdrs
Without CONFIG_AUTO_ZRELADDR being set the kernel needs a single
zreladdr for building zImages. Bail out if we detect multiple
zreladdrs without CONFIG_AUTO_ZRELADDR.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Stephen Boyd
3f8e288033 ARM: 7006/1: Migrate to asm-generic wrapper support
With d8ecc5c (kbuild: asm-generic support, 2011-04-27) we can
remove a handful of asm-generic wrappers in ARM code. Since the
generic version of sizes.h doesn't contain SZ_48M, we replace
the 4 users of SZ_48M with the equivalent SZ_32M + SZ_16M.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Acked-by: Krzysztof Halasa <khc@pm.waw.pl>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:12:40 +01:00
Barry Song
91c2ebb90b ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:51 +01:00
Barry Song
74d41f39a9 ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
this patch fixes the error in Rob Herring's
ARM: 7009/1: l2x0: Add OF based initialization
http://www.spinics.net/lists/arm-kernel/msg131123.html
it has been in rmk/for-next with commit 41c86ff5b

Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:40 +01:00
Barry Song
1caf30924f ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loop
using cpu_relax in busy loops is a well-known idiom in the kernel.
It's more for documentation purposes than technically needed here.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:36 +01:00
Rob Herring
8c369264b6 ARM: 7009/1: l2x0: Add OF based initialization
This adds probing for ARM L2x0 cache controllers via device tree. Support
includes the L210, L220, and PL310 controllers. The binding allows setting
up cache RAM latencies and filter addresses (PL310 only).

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:11:30 +01:00
Will Deacon
f73765fcb8 ARM: 7116/1: debug: provide dummy default option for DEBUG_LL UART choice
Defaulting to DEBUG_ICEDCC will cause systems to hang during boot unless
a hardware debugger is listening to the debug comms. channel.

This patch adds a dummy UART option as the default DEBUG_LL choice which
requires the platform to do the right thing.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Stephen Boyd
6996f425e5 ARM: 7097/1: debug: Move DEBUG_ICEDCC into the DEBUG_LL choice
DEBUG_ICEDCC support is just another DEBUG_LL choice and
selecting it along with other DEBUG_LL options doesn't make
much sense. Put it into the DEBUG_LL choice to avoid confusion.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Stephen Boyd
164acf96a9 ARM: 7096/1: debug: Add UART1 config choices
ARM patch 7072/1 (debug: use kconfig choice for selecting
DEBUG_LL UART) didn't notice that the Kconfigs relied on being
unselected to configure a different serial port. Since there is
no NONE option in a choice menu, explicitly add the other option
so that both serial ports can be selected.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Will Deacon
4f5ef9226a ARM: 7073/1: debug: augment DEBUG_LL Kconfig help to clarify behaviour
Enabled DEBUG_LL hardcodes the UART address into the kernel and results
in a non-portable kernel image. Since this option is only intended for
use when debugging early boot failures, supporting multiple platforms
in such a configuration is not the intended use-case.

This patch documents this limitation in the DEBUG_LL Kconfig help text,
so that users are aware of the portability restrictions that are associated
with enabling low-level debugging support.

Reported-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Will Deacon
17916b284e ARM: 7072/1: debug: use kconfig choice for selecting DEBUG_LL UART
Enabling CONFIG_DEBUG_LL (which is required for earlyprintk) hardwires
the debug UART address into the kernel, so that we can print before the
platform is initialised.

If the user inadvertently selects multiple platforms with DEBUG_LL
enabled, the UART address may not be correct and will likely cause the
kernel to hang in the very early stages of boot.

This patch, based on a skeleton from Russell, uses a Kconfig choice for
selecting the DEBUG_LL UART, therefore allowing the user to make a
choice about the supported platform when DEBUG_LL is enabled.

Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:03:03 +01:00
Jamie Iles
5a567d78c4 ARM: 7115/4: move __exception and friends to asm/exception.h
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.

v4:	- rebase to rmk/for-next
v3:	- remove redundant includes of linux/ftrace.h
v2:	- document the usage restricitions of __exception*

Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0af8aa0069 ARM: 7124/1: smp: Add a localtimer handler callable from C code
In order to be able to handle localtimer directly from C code instead of
assembly code, introduce handle_local_timer(), which is modeled after
handle_IRQ().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:44 +01:00
Shawn Guo
0b5a1b95dc ARM: 7123/1: smp: Add an IPI handler callable from C code
In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Shawn Guo
26a527e69d ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()
When Cortex-A9 MPCore resumes from Dormant or Shutdown modes,
SCU needs to be re-enabled.  This patch removes __init annotation
from function scu_enable(), so that platform resume procedure can
call it to re-enable SCU.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
267840f339 ARM: 7061/1: gic: convert logical CPU numbers into physical numbers
The GIC driver must convert logical CPU numbers passed in from Linux
into physical CPU numbers that are understood by the hardware.

This patch uses the new cpu_logical_map macro for performing the
conversion inside the GIC driver.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Will Deacon
d6257288c4 ARM: 7060/1: smp: populate logical CPU mapping during boot
To allow booting Linux on a CPU with physical ID != 0, we need to
provide a mapping from the logical CPU number to the physical CPU
number.

This patch adds such a mapping and populates it during boot.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Vincent Guittot
c9018aab8e ARM: 7011/1: Add ARM cpu topology definition
The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.

The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.

Changes since v4 :
*  Remove unnecessary parentheses and blank lines

Changes since v3 :
* Update the format of printk message
* Remove blank line

Changes since v2 :
* Update the commit message and some comments

Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-17 09:02:43 +01:00
Martin Schwidefsky
85055dd805 PM / Hibernate: Include storage keys in hibernation image on s390
For s390 there is one additional byte associated with each page,
the storage key. This byte contains the referenced and changed
bits and needs to be included into the hibernation image.
If the storage keys are not restored to their previous state all
original pages would appear to be dirty. This can cause
inconsistencies e.g. with read-only filesystems.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-10-16 23:27:46 +02:00
Linus Torvalds
8bc03e8f3a Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
  ARM: 7128/1: vic: Don't write to the read-only register VIC_IRQ_STATUS
  ARM: 7122/1: localtimer: add header linux/errno.h explicitly
  ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
  ARM: 7113/1: mm: Align bank start to MAX_ORDER_NR_PAGES
2011-10-16 13:08:27 -07:00
Zoltan Devai
f8be12d153 ARM: 7128/1: vic: Don't write to the read-only register VIC_IRQ_STATUS
This is unneeded and causes an abort on the SPMP8000 platform.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Zoltan Devai <zoss@devai.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Shawn Guo
bb1ac3ec95 ARM: 7122/1: localtimer: add header linux/errno.h explicitly
Per the text in  Documentation/SubmitChecklist as below, we should
explicitly have header linux/errno.h in localtimer.h for ENXIO
reference.

1: If you use a facility then #include the file that defines/declares
   that facility.  Don't depend on other header files pulling in ones
   that you use.

Otherwise, we may run into some compiling error like the following one,
if any file includes localtimer.h without CONFIG_LOCAL_TIMERS defined.

  arch/arm/include/asm/localtimer.h: In function ‘local_timer_setup’:
  arch/arm/include/asm/localtimer.h:53:10: error: ‘ENXIO’ undeclared (first use in this function)

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Will Deacon
29a541f6c1 ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.

Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: stable@kernel.org
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-10-15 11:04:22 +01:00
Florian Tobias Schandinat
ef26b7943c Merge branch 'for-florian' of git://gitorious.org/linux-omap-dss2/linux into fbdev-next 2011-10-15 00:19:52 +00:00
Florian Tobias Schandinat
07aaae44f5 Merge commit 'v3.1-rc9' into fbdev-next 2011-10-15 00:14:01 +00:00
Jan Beulich
72da0b07b1 x86: constify PCI raw ops structures
As with any other such change, the goal is to prevent inadvertent
writes to these structures (assuming DEBUG_RODATA is enabled), and to
separate data (possibly frequently) written to from such never getting
modified.

Reviewed-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-14 09:05:28 -07:00
Andi Kleen
30963c0ac7 x86, intel: Use c->microcode for Atom errata check
Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-10-14 13:16:38 +02:00
Andi Kleen
506ed6b53e x86, intel: Output microcode revision in /proc/cpuinfo
I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.

The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.

I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.

I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.

This turns out to clean up further code which already got this
information manually. This is done in followon patches.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-10-14 13:16:35 +02:00
Linus Torvalds
95bc156c62 Merge branch 'stable' of git://github.com/cmetcalf-tilera/linux-tile
* 'stable' of git://github.com/cmetcalf-tilera/linux-tile:
  tile: revert change from <asm/atomic.h> to <linux/atomic.h> in asm files
2011-10-14 16:59:11 +12:00
Linus Torvalds
2ad53110d6 Merge branch 'x86-urgent-for-linus' of git://tesla.tglx.de/git/linux-2.6-tip
* 'x86-urgent-for-linus' of git://tesla.tglx.de/git/linux-2.6-tip:
  x86: Default to vsyscall=native for now
2011-10-14 16:54:56 +12:00
Mika Westerberg
153b19a3b9 x86, mrst: use a temporary variable for SFI irq
SFI tables reside in RAM and should not be modified once they are
written.  Current code went to set pentry->irq to zero which causes
subsequent reads to fail with invalid SFI table checksum.  This will
break kexec as the second kernel fails to validate SFI tables.

To fix this we use temporary variable for irq number.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-10-14 16:53:27 +12:00
Kuninori Morimoto
f427eb64f4 usb: gadget: renesas_usbhs: support otg pin control
some renesas_usbhs device is supporting OTG external device interface.
In that device, it is necessary to control PWEN/EXTLP on DVSTCTR.
This patch support it.
But renesas_usbhs driver doesn't have OTG support for now.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-10-13 20:41:47 +03:00
Nicolas Pitre
0cdc8b921d ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.

The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:53:53 -04:00
Nicolas Pitre
48de58e34e ARM: mach-s5p64x0: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:52 -04:00
Nicolas Pitre
b4be3999d1 ARM: mach-s3c64xx: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:51 -04:00
Nicolas Pitre
c039bad00f ARM: plat-mxc: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:50 -04:00
Nicolas Pitre
17dea45adb ARM: mach-prima2: remove mach/memory.h
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-10-13 12:49:50 -04:00